difference between 180 nm and 90 nm interms of all aspects

[umaram]

hi
for a transistor in 90 nm if the L=0.2 micro meter and width is 4 times of length to achieve required transfer characteristics what could be the changes to be made in 180 nm.

 

[rahdirs]

Are you asking for W/L ratio & channel length of 180 nm transistor so that it has same saturation region profile as 90 nm transistor.

 

[umaram]

Hi,
In my project I am working on IEEE based .topic is ANALOG IMPLEMENTATION OF A SIGMOIDAL FUNCTION USING CMOS IN 90nm TECHNOLOGY
but we are trying to implement in 180 nm cadence.
concept is that they are following is
[PLEASE CHECK ATTACHED PAPER NAMED P1]
current is the input and voltage is output at the same node as shown in paper
and in the graph of sigmoidal function they have current ranging from -6uA to +6uA
Libraries used: gpdk180
Instances used : nmos, pmos, etc.
Pins used : Input,output.
Proper connections are established between instances in the circuit design.


In 180 nm we are trying to these things
Target Specifications:

Cmos technology to be used: 180 nm.
Supply voltage : 1.8 or 2.5v
No. of transistors 6
Testing region for linearity:
Targeted max. variation wrt ideal function. -6 to +6 microamperes.
Max. error of 8% or better.
Testing range for temperature:
Targeted output voltage variation: -55 to 125 degree celcius
Less than 5% from ideal function.
Initial estimation of total area consumed by the circuit in 180nm tech. <15 micrometer square.

 

[erikl]

I'm not sure if this source follower architecture works well in a 180nm process - this depends very much on the Vsupply/Vth0 ratio and Vth0_n/Vth0_p symmetry. Instead of the simple source follower I'd prefer a real gain stage with appropriate resistive current feedBack, something like this: View attachment sigmoidal.pdf

For simulation I've used 180nm models with symmetric Vth0. Could be different with the gpdk180nm models.