difference b\w latch and flipflop

[the moon is back]

hi, guy s pls explain me how does a flipflop is different from latch?

thank u

 

[subbuindia]

hi, guy s pls explain me how does a flipflop is different from latch?

thank u

There are 2 types of circuits:

1. Combinational

2. Sequential

Latches and flip flops both come under the category of "sequential circuits".

Difference: Latches are level-sensitive, whereas, FF are edge sensitive. By edge sensitive, I mean O/p changes only when there is a clock transition.( from 1 to 0, or from 0 to 1)


If u can observe the flip flop and latches diagrams,




1)flip flops take twice the number of gates as latches

2) so automatically delay is more for flip flops

3)power consumption is also more for flip flops


Hope, u got clear your doubt.........

 

[jwdonal]

To expand on subbuindia's description, a flip-flop is essentially a "synchronous latch" (i.e. a latch with a clock input and an edge-triggered output). An asynchronous latch is called a "transparent latch" and is level-sensitive rather than edge-sensitive.

In addition, 99% of the time you should avoid asynchronous (transparent) latches in your code, most especially if it is meant to be synthesizable and you want to put it in an ASIC or FPGA for instance. Synth tools will report a bazillion warning messages if you've got asynch latches in your design. Asynch latches are bad news and most (all?) FPGAs must emulate the "behavior" of an asynch latch using additional logic components in the chip since they don't have any "real" asynch latches.

Async latches are usually the undesired result of not including an 'else' clause in your if/else construct or from forgetting to include the 'default' case in a case statement. For example:

always @*
  if (my_input == 1)
    my_output = 0;

--OR--

always @*
  case (my_input)
  1: my_output = 0;
  endcase

Either of the above will create a latch during synthesis because the FPGA/hardware must "remember" the previous value of my_output when my_input changes to 0. So another way of thinking of a latch is a 'memory'. To fix the above to remove the latch condition you could do this:

always @*
  if (my_input == 1)
    my_output = 0;
  else
    my_output = 1;

--OR--

always @*
  case (my_input)
  1: my_output = 0;
  default: my_output = 1;
  endcase

--OR-- (a much simpler way)

assign my_output = ~my_input;

Any of the above will just synthesize to an inverter.

 

[verylsi]

Both the above replies are great, I would like to add an image for better understanding..


Latches are specially not recommended for FPGAs bcz Fpga has predefined structure for FF but there is no predefined structure for latches in FPGA.
Also timig issues in FF can be detected and solved using timing analysis but there is very little control over timing delays and race condion generated due to latches.
also the term set up and hold time issues in Flip flop are replaced by recovery time and removal time in latches respectively.

One important note I would like to add is that although no one recommend latches but if you are an expert and you know exactly what you are designing then latches are far better in performance than FF as they consume much less power and are twice as fast than FF. But again, one must be an expert to implement a latch based design.

 

[the moon is back]

jwdonal, async. latch means latch which doesn't have clk signal and operates only on change in inputs, isn't it?

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thank u everybody for your useful discussion.

 

[jwdonal]

jwdonal, async. latch means latch which doesn't have clk signal and operates only on change in inputs, isn't it?

Correct. Async latch output changes to match the value of the input after some combinatorial delay (which would be specified in the latch's datasheet).