differance between verilog and system verilog

[renoz]

hi



i want to know the differance between verilog and system verilog


thankz advance

 

[blooz]

System verilog has features of verilog besides many useful features of VHDL ,System verilog has many objected oriented based features ,system verilog is currently a leading verification language .Actually it's a HDL and HVL .it has many Advanced features than Verilog and primarily used for verification ,Assertion based ,coverage driven etc .Currently most of the mature synthesis tools support verilog /VHDL only but soon System verilog Synthesis will be implemented .Ideally you should learn Verilog before system verilog ,and VHDL too if possible .If you have good verilog coding skills and have learned at least any one of oops languages like c++/java then system verilog learning will be easier .
Verilog is currently the leading HDL for system Design along with VHDL .

 

[renoz]

thank you for your valuable reply

 

[blooz]

More about system verilog

h**p://www.systemverilog.org/

Tutorials

h**p://www.asic-world.com/systemverilog/tutorial.html


h**p://www.systemverilog.in/

books

System verilog for Verification -Chris Spear
A practical guide for System verilog for Assertion -srikanth Vijaraghavan ,meyyappan ramanathan
Writing Testbenches Using System verilog -Janick bergeron