diff btw bit and std_logic in vhdl

[kil]

std_logic in vhdl

Hi all,

whats the diffrence between BIT and Std_ulogic and Std_logic and how the bit and std_logic differe after the synthesis.

Thanks & Regards
KIL

 

[vinodkumar]

vhdl std_logic

As i know,

Bit-0,1 only 2 values..
Std_logic 7 values..
how many values we model between 0 and 1 level...

 

[angelote]

std_logic values

As vinodkumar said, BIT has 2 values: '0' and '1'.

STD_LOGIC has 9 values: 'U', 'X', '0', '1', 'Z', 'W', 'L' ,'H' and '-'.

I know the meaning of some of them:
U = unknown (*)
X = collision - a multisource line is driven '0' and '1' simultaneously (*)
0 = logic 0 (*)
1 = logic 1 (*)
Z = high impedance (*)
W = (i don't know)
L = driven low weakly
H = drivel high weakly
- = (i don't know)

The values marked (*) are common y real logic simulation.

With BIT you use an ideal logic world, and with STD_LOGIC you have a more real behaviour of logic, and allows you to simulate tri-state signals.

I never heard about STD_ULOGIC.

The only difference I see between BITY and STD_LOGIC in synthesis is the 3-state generation.

 

[salma ali bakr]

bit to std_logic vhdl

always use std_logic and std_logic_vector...

 

[kil]

vhdl std_logic x

Hi,

Which is the actual cases where we encounter to use all the 9 Strengths... does the Different Strengths tell the REAL strength of the signal but in digital design we always go with either 1 ,0 or high impedence right.. when we encounter the other states right weak 0, weak 1 states.... do this any thing to do with the noise margin of the CMOS circuit .......

Thanks
KIL

 

[angelote]

vhdl bit vs std_logic

No.

Weak states are like a pull up or pull down resistor. A weak 0 maintains its value ina a multisource signal until another source puts a strong 1, for example.

I'm not sure, but I think that in real FPGA internal circuits, a weak level is not synthesizable, multisource signals are not allowed, neither bidirectional lines, neither high impedance states.

 

[SHRIRAM_GAUR]

Re: std_logic in vhdl

'U' --> Uninitialized
This is the default initial value for objects of type STD_LOGIC. If no initial value is specified in the declaration of an object, the object acquires value 'U' after the initialization of simulation.

'X' --> Forcing Unknown
'X' results if two or more opposing forcing values ('0' and '1') drive a signal of type STD_LOGIC.

'0' --> Forcing 0; also known as Strong logic '0' state.
'1' --> Forcing 1; also known as Strong logic '1' state.

'Z' --> High Impedance...High impedance state.

'W' --> Weak Unknown
'W' results if two or more opposing weak values ('L' and 'H') drive a signal of type STD_LOGIC.

'L' --> Weak 0; Weak logic '0' state.
'H' --> Weak 1; Weak logic '1' state.

'-' --> Don't care; Don't care state.

Regards,
Shriram Gaur

 

[shanmugaveld]

Re: std_logic in vhdl

Check below link
what is the difference between the types std_logic and std_ulogic