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diff between verilog and VHDL

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N vijay kumar

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hi every one,

I have a doubt that chasing me from my first class of verilog, i.e, what is diff between verilog and VHDL.is both are difference in total method or the difference is only syntaxes.
i want to know the strengths and -ve of both of them.

can any one please help me.
 

ckshivaram

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Verilog and VHDL are Hardware Description languages that are used to write programs for electronic chips. These languages are used in electronic devices that do not share a computer’s basic architecture. VHDL is the older of the two, and is based on Ada and Pascal, thus inheriting characteristics from both languages. Verilog is relatively recent, and follows the coding methods of the C programming language.

VHDL is a strongly typed language, and scripts that are not strongly typed, are unable to compile. A strongly typed language like VHDL does not allow the intermixing, or operation of variables, with different classes. Verilog uses weak typing, which is the opposite of a strongly typed language. Another difference is the case sensitivity. Verilog is case sensitive, and would not recognize a variable if the case used is not consistent with what it was previously. On the other hand, VHDL is not case sensitive, and users can freely change the case, as long as the characters in the name, and the order, stay the same.

In general, Verilog is easier to learn than VHDL. This is due, in part, to the popularity of the C programming language, making most programmers familiar with the conventions that are used in Verilog. VHDL is a little bit more difficult to learn and program.

VHDL has the advantage of having a lot more constructs that aid in high-level modeling, and it reflects the actual operation of the device being programmed. Complex data types and packages are very desirable when programming big and complex systems, that might have a lot of functional parts. Verilog has no concept of packages, and all programming must be done with the simple data types that are provided by the programmer.

Lastly, Verilog lacks the library management of software programming languages. This means that Verilog will not allow programmers to put needed modules in separate files that are called during compilation. Large projects on Verilog might end up in a large, and difficult to trace, file.

Summary:
1. Verilog is based on C, while VHDL is based on Pascal and Ada.

2. Unlike Verilog, VHDL is strongly typed.

3. Ulike VHDL, Verilog is case sensitive.

4. Verilog is easier to learn compared to VHDL.

5. Verilog has very simple data types, while VHDL allows users to create more complex data types.

6. Verilog lacks the library management, like that of VHDL.
 

N vijay kumar

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"""" Verilog lacks the library management of software programming languages. This means that Verilog will not allow programmers to put needed modules in separate files that are called during compilation.""""

i dint get that, as we can write modules in separate files in verilog and by including them together or by specifying both the files while compilation we can compile them.
that means we can write code(modules) in different files.

---------- Post added at 13:39 ---------- Previous post was at 13:29 ----------

how it is in VHDL.
 

Alexium

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Personaly, I find VHDL easier than Verolog, though I'm more of a C++ programmer than HDL developer. Probably because I've learnt VHDL first, but still - now that I know both languages I prefer VHDL.
 

TrickyDicky

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At the end of the day, they both produce the same thing - registers and gates.

---------- Post added at 08:31 ---------- Previous post was at 08:31 ----------

Personaly, I find VHDL easier than Verolog, though I'm more of a C++ programmer than HDL developer. Probably because I've learnt VHDL first, but still - now that I know both languages I prefer VHDL.

People that learn C first tend to prefer Verilog.
 

Alexium

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At the end of the day, they both produce the same thing - registers and gates.
Can't argue with that!

People that learn C first tend to prefer Verilog.
I did learn C, then VHDL, and then Verilog.
You can't define enum type in Verilog, how are you supposed to describe FSM? Manually code the states? That's BS, I think. And Verilog doesn't have generic constants (correct me if I'm wrong). I'll better stick with VHDL.
 

N vijay kumar

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hi,
i dont know how we write code in VHDL.
can any one give code for a single task in both VHDL and verilog so that i can easily understand from that.
and i can also get the similarities and differences in coding between them.
 

zel

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example of 8 bit count-up counter for VHDL and Verilog

VHDL
////////////////////////////////////////////
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity up_counter is
port (
cout :eek:ut std_logic_vector (7 downto 0); -- Output of the counter
enable :in std_logic; -- Enable counting
clk :in std_logic; -- Input clock
reset :in std_logic -- Input reset
);
end entity;

architecture rtl of up_counter is
signal count :std_logic_vector (7 downto 0);
begin
process (clk, reset) begin
if (reset = '1') then
count <= (others=>'0');
elsif (rising_edge(clk)) then
if (enable = '1') then
count <= count + 1;
end if;
end if;
end process;
cout <= count;
end architecture;

VERILOG
////////////////////////////////////////////
module up_counter
(
output reg [7:0] cout,
input enable,
input clk,
input reset
);

always @(posedge clk) begin
if (reset)
cout <= 8'b0 ;
else
cout <= (enable) ? cout + 1;
end

endmodule
 
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