Diff b/w unknown value 'X' and high impedance value 'Z'

[carrot]

high-impedance(z) and unknown (x)

Hi,

What is the difference between unknown value 'X' and high impedance value 'Z'
When is each one of them used?

 

[wwfhm2002]

for example, if you use tri-state buf, then there will be 'Z' value if enable signal is deactive. And 'X' is happen when there is timing violation.

'X' means '0' or '1' . 'Z' means neither '0' nor '1'.
Normal we avoid use them in digital logic.

 

[maksya]

'Z' - high impedance state. 'X' state means that we can't determine what is the logic state on the output of a circuit.

 

[shankarmit]

Z means high impedance i.e., not connected to '0' or '1' left floating...comes when using tri state buffer..

X occurs when a signal is assigned value '0' and when you force value '1' into the signal..


Regards
Shankar

 

[anilkumarv]

Z means high impedance state. The output is neither 0 or 1 i.e the there is no connection to the port(in terms of synthesis).
X refers to toggling of values . It is either 0 or 1

 

[vcnvcc]

Just remember, Either or & Neither nor

X - Either 0 or 1
Z - Neither 0 nor 1..

 

[funster]

a floating wire is high Z;

a active output with unknow state is X.

best regards

Hi,

What is the difference between unknown value 'X' and high impedance value 'Z'
When is each one of them used?

 

[anilkumarv]

High impedance (Z) occurs when a particular port is not connected.
X occurs when there is a timing violation.

 

[aland]

Use Z to electricaly disconnect the *output* from the bus so another signal can control it ( high impedence)

use X to denote a dont care state on the *input*. ie if a=1, b=0, c=X then y=a.b.c would reduce to y=a.b (we dont care about c)

 

[rajesh9999]

In response to the above poster, X is not "dont care" but "unknown" value. I think you are confusing with Karnaugh maps where dont cares are denoted by X. If an input to a gate is X (unknown) then the output is also X (unknown). Unfortunately the term X is used interchangebly. For example in writing case statements in verilog, x denotes "dont care" whereas in simulation x denotes "unknown"

 

[gaonkc]

In logic design, "x" state mean that logic fight is exist in some noed. "z" state mean that no driver on this node.

 

[Shurik]

X - This is a potential between logical "0" and "1"
Z - This connection is broken off

https://obrazki.elektroda.pl/48_1158073496.jpg

 

[sawaak]

Hi,
'Z' means the net is floating, it is not connected to any other signal.
'X' means there is a contention b/w signals, that is if a signal is at '0' or '1' and you try to force the same signal to '1' or '0', then the simulator has no way to determine what should be the value of that net, hence it displays 'x', unless there is a wired AND or wired OR connection.

thanks
sawaak