DIE SIZE( SOC ENCOUNTER)

[vlsitechnology]

die size estimation

Can anyone tell me how to calculate the die size ?
In encounter it is giving the coordinates directly in DEF FILE but how to calculate it manually can anyone explain me?

 

[fpga_asic_designer]

there is no need to calculate die size after you get the def file, since the number is there already.

it is good to estimate the die size in the spec-defining stage and watch the die size in synthesis and STA stage.

Consider if it's a pad limited chip. If yes, Die Size(um2)=SUM(one side pad widths)*SUM(one side pad widths)
If core limited, Die Size(um2)= SUM(Module Gate Counts)*Technology(Size of NAND2X in certain technology)*(1+routing efficiency)

No one can estimate die size correctly and accurately in any stage. Definitely need a netlist to do floorplan so as to estimate die size. There should be enough margin in die size estimation. Include margin for adding logics, DFT, pin scan logics, HFN, CTS etc...

i am not a floorplan guy, this is what i know as a front end.

 

[sekapr]

def file =

DIA AREA = (X1 Y1) (X2 Y2);


die size = SQRT{(X2-X1)+(Y2-Y1)}

 

[xinsu]

If you just want know the die size based on fixed floorplan def,you can follow sekapr answer,if you want to estimate die size,you should try initial floorplan based on your spec.

 

[rakesh1234]

Can you please more elaborate more on this ???

Consider if it's a pad limited chip. If yes, Die Size(um2)=SUM(one side pad widths)*SUM(one side pad widths)
If core limited, Die Size(um2)= SUM(Module Gate Counts)*Technology(Size of NAND2X in certain technology)*(1+routing efficiency)