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DFT workflow in the ASIC design

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always@smart

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Could anyone guide me the Design For Test flow in the ASIC design?? what tools to be used??

Thank you

regards :p
 

always@smart

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turbofault dft

What I have ever seen and experienced is the Syn*psys DC's buit in scan insertion command, but pls tell me more bout the DFT, methodology and whatever.........
 

joe2moon

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memory testing in dft

DFT stands for Design-For-Test !

So, most important of all is:
"take test into consideration while doing the design !"

The EDA tools, such as $yn0psys' DFT C0mpiler, Ment0r's DFTAdvisor, or
$yntest's Virtual Sc@n, can only provide the "structured-DFT" solution ---
the scan-chained design.

ps:
The purpose of inserting scan chain is to
make ATPG task more easier.
(Since sequential ATPG is not an easy job and
the test coverage may be very low.)
 

joe2moon

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fastscan dft advisor eda tools overview

*** Plan before execution ***
--------------------------------
Design: Design plan
Verification: Verification plan
Test: Test plan
--------------------------------
Design plan: function, timing, power and so on.
Verifiation plan: verification methodology used, code coverage, functional coverage, ...
Test plan: test strategy used, test mode definition, test coverage, fault coverage
--------------------------------
Test strategies:
* Memory:
- BIST: BIST algorithm, such as March,...
- Others:
* Analog blocks:
- PLL:
- ADC:
- DAC:
* Digital blocks:
- Functional testing: (-> run fault simulation or not)
- ATPG
+ scan
# full scan
# partial scan
* Whole chip:
- Boundary scan
-
--------------------------------

See the following also:
"Reduce test costs throughout the design cycle"
www.eedesign.c0m/story/OEG20030616S0108
 

joe2moon

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scan check for dft

Some of the EDA Tools:
www.mentor.c0m/dft/products.html
- BSDArchitect - boundary scan
- DFTAdvisor - test synthesis
- FastScan - ATPG
- LBISTArchitect - logic BIST
- MBISTArchitect - memory BIST
- TestKompress - test compression

www.syntest.c0m/
- DFT- PRO Plus - A Comprehensive Package of DFT Tools
- VirtualScan - Virtual Scan Synthesis and ATPG
- TurboBIST - Built-in Self-Test
- TurboBSD - Boundary Scan
- TurboCheck - Testability Analysis
- TurboFault - Fault Simulation

www.logicvision.c0m/products/index.html
- Chip Test Assemble - boundary scan
- Logic BIST - Embedded IP test
- IC Memory BIST - Embedded memory test
- PLL BIST - Embedded PLL test

www.synopsys.c0m/products/test/test.htm
- BSD Compiler - boundary scan
- DFT Compiler - test synthesis
- TetraMAX® ATPG - ATPG
 

jobnom99

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tetramax boundary scan

This is My synopsys DFT flow

1. HDL design considering Testing
==> you can check Synopsys RTL TESTDRC check with DFT compiler
==> Memory : Memory BIST logic insertion

2. Synthesis considering Scan : DC Compiler
==> compile -scan ( pre_compiled with scan)
==> this command make F/F ==> scan F/F
==> check_test or check_dft : check DFT Violation Rule

3. SCAN insertion & make chain : Synopsys DFT compiler
==> insert_scan or insert DFT
==> this command make scan chain
of course , we have to cofigure scan chain

4. BSD(JTAG) insertion with Synopsys BSD compiler
==> insert_bsd
==> you can insert JTAG before synthesis.
==> Make BSD vector with BSD compiler

5. ATPG with Synopsys Tetramax

==> make ATPG vector with Tetramax
==> get fault exact coverage
==> if you want , you can fault_simulation.

6. Simulaiton ( ATPG , MBIST , JTAG)

==> simulate all vector with your simulator ( ncsim or vcs or others)
 

joe2moon

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create a partial scan chain

>>> you can check Syn0psys RTL TESTDRC check with DFT compiler

From my experience, the result of RTL DRC is not so good, .ie.
the correlation between the (RTL) DRC and the DRC with
gate-level netlist is not so close.
---------------------------------------------------------------------------------
Just for your reference:

Dataquest FY 2001 ATPG Market
Mentor Fastscan (61%)
Synopsys TetraMAX (31%)
others (8%)

Dataquest FY 2001 Scan Insertion Market
Synopsys DFT Compiler (91%)
Mentor DFT Advisor (7%)
others (2%)

h**p://www.deepchip.c0m/items/snug03-12.html
 

nozone

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how to create a partial scan chain

which one is better, now I only have DFT from ment0r
 

joe2moon

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full scan dft compiler

For scan chain insertion:
It's beeter to stitch the scan chain(s) under Physical C0mpiler's environment.
Since it can consider the physical location during chaining.
So in this domaim, DFT C0mpiler wins.
[invoke DFT C0mpiler from Physical C0mpiler]
------------------------------------------------------------------------------

For ATPG:
pattern generation & pattern compression
It seems that Ment0r does a beeter job.
------------------------------------------------------------------------------
 

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