[DFT] What is fault grading?

[maulin sheth]

Hello All,

can anyone help me for understanding the fault grading concept and application?

Thanks & Regards,
Maulin

 

[dave_59]

Logic fault grading is the process of determining what percentage of list of particular manufacturing defects (faults) will be detected if you run a test or series of test on a device. Fault grading does not verify that a device meets a design specification, only that the device was manufactured according to the instructions used to manufacture the device.

This paper describes the concept very well, and has not changed that much in so many years.

Automatic test pattern generation algorithms have largely replaced the need for fault grading, which is very CPU intensive.

 

[maulin sheth]

Thanks.
But, If it is the percentage of list of particular manufacturing defects (faults), than it is same as Test coverage (detected faults /total faults )?
or what do you mean by list of particular manufacturing defects...it is same as the total faults or anything else?
Can I know why you use the word logic fault grading?

 

[rca]

Fault grading for me is to simulate (in ATPG tool), the stuck pattern when you are in bridge mode to reuse the stuck patterns to now how many bridge fault are already covered, and then the ATPG tool generate the required new bridge fault to reach the target fault coverage. Then by exercising the stuck and bridge patterns on the DUT, you will reach the both coverage with a limited number of bridge pattern for example.

 

[maulin sheth]

Thanks RCA,
I also get this concept through google search.
What I know is, Suppose I have the patterns for transition faults, now I check that how many SA faults are covered through this Transition patterns, thn after only remaining SA faults are targeted for ATPG.
Correct me if any misunderstanding by me.

 

[dave_59]

I used the term "logic fault" for those faults that can be represented by changing the behavior of a digital logic simulation. These are stuck-at, bridging and transition faults. Other types of faults are very difficult to model without analog modeling in the frequency domain. Total faults is the total number of manufacturing defects a particular simulation has chosen to model. For example, most simulators use a single SA fault model. But you could also choose to model double and triple stuck-at faults if you had a tool that supported it as well as the patience to wait for the simulation results.

 

[maulin sheth]

Thanks Dave SIr,
Buf If fault grading is the percentage of list of particular manufacturing defects (faults), than it is same as Test coverage (detected faults /total faults ) or not?

 

[dave_59]

I guest so as long as (particular_set_of_manufacturing_defects == total_faults). I usually think of the term "test coverage" to apply to the total of all coverage metrics, which includes code coverage and functional coverage, and not specifically fault coverage. There are no hard definitions in this area, only industry practices.