Which DFT tool can generate the necessary input assignment of the circuit?
If no tool can do that, which DFT tool can generate the non-compress test patterns for the circuit?
Hmmm.....
I detail the features I wanted.
I need the test patterns of every single fault at the circuit and ATPG is able to generate in one pass.
I mean that I don't need to give the constraint of every fault and run the ATPG again.