Yes i agree, that the spare cells would be some where present in a CHIP, which doesn't initially put up in a scan chain.
Once an ECO is needed and by that time, we use this spare cells, flops, and put into the scan chain as well, and regenerate vectors for ATPG.
with this i have new doubt born,
whether we have some geometry pre fixed by a Top level designer to place these spare cells or flops in our CHIP, because we dont see a spare in pre_layout Netlist. Am i right?
So, we do have a extra area (small/large - depending on the spare cells) to be present in a CHIP. My pre layout AREA Report will not cover this spare cells intially, but after Layout has inserted, it accounts for area? Will this doesnot disturb my chip size, in terms of area? (later we can discuss abt power). Can any one help on this plz?
Hariharan GB