For normal 'stuck-at' scan patterns, the shift clock is normally provided by the same source (the ATE). Using some fancy tricks, you can, for at-speed scan, enable the internal clocks to do the capture. This is usually done only if the ATE cannot provide a fast enough clock for at-speed capture, and this must be specifically designed in the clock generation circuitry.
But the ATPG tool, must understand, in any case, how to control those clocks in a deterministic way, or else it can't generate patterns.
Other than the clock-gating design mentioned above, at-speed scan is normally dealt with at ATPG time, especially with regards to mult-cycle paths, false paths and clock domain crossings. These obviously can't be tested at-speed, and are usually masked out.