Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

dft question (pls answer )

Status
Not open for further replies.

gold_2007

Member level 1
Joined
Aug 2, 2007
Messages
40
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Location
bangalore
Activity points
1,510
can any one tell me what are the different information does a designer give to dft person along with the netlist and library.
 

Thinkie

Full Member level 3
Joined
May 26, 2005
Messages
177
Helped
18
Reputation
36
Reaction score
4
Trophy points
1,298
Activity points
2,242
Also give the clock domains, reset strategy, latches, combinatorial loops if any
 

    gold_2007

    Points: 2
    Helpful Answer Positive Rating

mujju433

Full Member level 3
Joined
Jun 2, 2007
Messages
174
Helped
4
Reputation
8
Reaction score
2
Trophy points
1,298
Activity points
2,293
They will give u clock and reset.. bcoz these are the most important thing u have to consider and u have to take care about the synchronism..
Muxes, clock ,reset are the most important thing for a dft designer to choose
 

    gold_2007

    Points: 2
    Helpful Answer Positive Rating

stormwolf

Advanced Member level 4
Joined
Jan 3, 2004
Messages
113
Helped
12
Reputation
24
Reaction score
0
Trophy points
1,296
Activity points
777
critical path, sta scripte
 

    gold_2007

    Points: 2
    Helpful Answer Positive Rating

rameshsuthapalli

Full Member level 3
Joined
Jun 27, 2006
Messages
155
Helped
24
Reputation
48
Reaction score
7
Trophy points
1,298
Location
bangalore,india
Activity points
2,129
Hi All,

Along with the above information they will also tells the power domain info and jtag register configurations that we need's to do for the required modes and controlls..
regards,
ramesh.
 

    gold_2007

    Points: 2
    Helpful Answer Positive Rating

gold_2007

Member level 1
Joined
Aug 2, 2007
Messages
40
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Location
bangalore
Activity points
1,510
rameshsuthapalli said:
Hi All,

Along with the above information they will also tells the power domain info and jtag register configurations that we need's to do for the required modes and controlls..
regards,
ramesh.
Thanks ramesh and all
 

vlsichipdesigner

Full Member level 2
Joined
May 9, 2007
Messages
134
Helped
16
Reputation
32
Reaction score
9
Trophy points
1,298
Location
India
Activity points
2,367
Dear Designer

my 2 cents in this discussion

1. Verilog netlist
2. STIL/TPF file (Standard Test Information file/Test Protocol file) , a procedure file generated from the DFT test compiler report
3. List of flip-flops in each scan-chain.
4. Scan input and scan output signals
5. Scan clock name
6. Signal to control the resets.
7. Scan mode/Test mode signals
8. Flops not part of chain and any reason.

Praise the Lord.

best regards,
www.vlsichipdesign.com
[Learn ASIC Chip Concepts both frontend and backend for free]
 

    gold_2007

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top