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They will give u clock and reset.. bcoz these are the most important thing u have to consider and u have to take care about the synchronism..
Muxes, clock ,reset are the most important thing for a dft designer to choose
1. Verilog netlist
2. STIL/TPF file (Standard Test Information file/Test Protocol file) , a procedure file generated from the DFT test compiler report
3. List of flip-flops in each scan-chain.
4. Scan input and scan output signals
5. Scan clock name
6. Signal to control the resets.
7. Scan mode/Test mode signals
8. Flops not part of chain and any reason.