Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[DFT] Power reduction in chain test

Status
Not open for further replies.
M

maulin sheth

Advanced Member level 2
Advanced Member level 2
Joined
Oct 24, 2010
Messages
502
Helped
90
Reputation
179
Reaction score
90
Trophy points
1,318
Location
Bangalore, India
Visit site
Activity points
4,161
Hello All,

Can any one brief me about power reduction techniques we can do for chain test pattern?
And what are the switches that takes care power reduction in cadence Encounter True time ATPG.

Thanks & Regards,
Maulin
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top