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DFT: is there a need to constraint test ports(SE, SI, TM, SO)?

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irun2

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Hi there,
I'm not sure if I should constrait the test ports, after compile -scan and insert_dft, STA show there're lots of hold time violations related to SE(scan_enable) port. How can I fix that?
Besides, if I want to simulate the test mode, should I use modelsim or any other tools?
 

rca

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1- checks if you forgot to apply a disable_path on SE path. As you control this signal externaly, you don't need to have hold time fix.
2-all verilog simulator + sdf back annotation should be able to simulate the test mode
 

irun2

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1- checks if you forgot to apply a disable_path on SE path. As you control this signal externaly, you don't need to have hold time fix.
2-all verilog simulator + sdf back annotation should be able to simulate the test mode

Thanks for the advice! I am thinking if the ATPG tool tetraMAX can run the simulation as one DFT guide has mentioned it.
 

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