Nitin1245
Newbie level 3
1. EDTbypass is passing. EDT chain patterns are failing. What could be the reasons.
2. Two subchips are there. Shifting power is huge. HOw to reduce power dissipation?
What are the options you have, without affecting coverage and test time? (HW or SW
options).
3. Setup vioations are there in your design. Which patterns would fail? (s@ or @speed?)
4. Hold vioations are there. Which patterns would fail?
5. Hold vioations are there. Which patterns would fail?
6. Two flops will have the same values during shift. Whats the effect of it?
7. Where do we use parallel testbench? Whats the use of parallel simulations?
8. If you have simulations failures, what are the things you would look at?
9. In synthesis, if area is not meeting the target, what would you do?
10. If some flops in two clock domains are failing, (S@ patterns), and those failures are
expected.HOw would you make them pass them on silicon? (no design changes are
allowed.
11. Atspeed coverage is always less than STUCK-at coverage. Why?
12. P1500? are you aware of it?
13. AND gate - optimal input pattern set to detect all S@ faults.
14. What are EDT aborted faults?
15. DRCs in ATPG
2. Two subchips are there. Shifting power is huge. HOw to reduce power dissipation?
What are the options you have, without affecting coverage and test time? (HW or SW
options).
3. Setup vioations are there in your design. Which patterns would fail? (s@ or @speed?)
4. Hold vioations are there. Which patterns would fail?
5. Hold vioations are there. Which patterns would fail?
6. Two flops will have the same values during shift. Whats the effect of it?
7. Where do we use parallel testbench? Whats the use of parallel simulations?
8. If you have simulations failures, what are the things you would look at?
9. In synthesis, if area is not meeting the target, what would you do?
10. If some flops in two clock domains are failing, (S@ patterns), and those failures are
expected.HOw would you make them pass them on silicon? (no design changes are
allowed.
11. Atspeed coverage is always less than STUCK-at coverage. Why?
12. P1500? are you aware of it?
13. AND gate - optimal input pattern set to detect all S@ faults.
14. What are EDT aborted faults?
15. DRCs in ATPG