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DFT is Design For testability. This technique is used to check whether manufacturing process has added any defects in the chip. DFT insertion means inserting an additional logic to improve the testability of the internal nodes of the design. Testability is the ability with which you can "communicate" with an internal node through the primary input and output pins.
You can use DFT compiler from Synopsys. There are tools from cadence and mentor also.
The flow : Before synthesizing you should check if the design is meeting the DFT requirements, if it is meeting then the tool will do appropriate modifications and generates the netlist. In some tools you do have an option to fix the DFT violations automatically .
If you only want insert the scan chain, all synthesis tool could do this.
If you want to insert Bist, dft compressor, you need special tool, like dft compiler....
After that, you need an ATPG tool to generate the patern, like tetramax or fastcan or other. I case your used a compressor, you must need to used the same tool family.
If you only want insert the scan chain, all synthesis tool could do this.
If you want to insert Bist, dft compressor, you need special tool, like dft compiler....
After that, you need an ATPG tool to generate the patern, like tetramax or fastcan or other. I case your used a compressor, you must need to used the same tool family.
I am new to DFT - and understanding it from top level first.
Please give your comments for my questions
1. Lets assume I wanted to add scan chain in my design, so I'll be using DC or DFT compiler?
"rca" - you are saying DC will do, it means I dont need DFT compiler at all?
Along with that you are saying about BIST - it means on top of scan chain, if I want to add BIST, then DFT compiler is useful?
Kindly give fundamental idea when to use DFT compiler? If I dont have it, then only DC will solve my purpose?
1) DFT compiler is a part of DC..but we require licence for DFT Compiler. So if you want to add scan chain than you can do it by DC if DFT is along with DC.
BIST is seperate from scan design....there is not any much relation between scan design and BIST. We can say that ,these are two different methods.
DFT compiler we mostly used after gate level conversion for scan design. Different different techniques have different flows.
DC and DFT Compiler are two different tools. DFT Compiler runs in the DC Shell. DC tool can only replace normal flops with scan equivalents. Thats the closest thing it can do for a DFT Engineer. Once the netlist has flops which are scan replaced, we call it scan ready netlist. Now you can use this for either inserting the traditional scan chains(for which you use DFT Compiler) or LBIST (BIST is too generic). For LBIST there are couple of other tools and I haven't seen DFT Compiler inserting a bist! (Correct me if I am wrong).
Maulin, I agree that BIST is a different flow all together, but to insert BIST also we need scan replaced flops in the design and DC can do that for us!
Thanks ranger for correct guidance....
But we can add MBIST at rtl level without Scan flops...but if we talk about LBIST...thn its fine....but for MBIST,does not require Scan FFs..pl correct me if any mis understanding...
Thanks ranger for correct guidance....
But we can add MBIST at rtl level without Scan flops...but if we talk about LBIST...thn its fine....but for MBIST,does not require Scan FFs..pl correct me if any mis understanding...
Yeah I meant only for LBIST and BIST is a generic thing. You can have BIST for functional patterns also (very specific cases). As you said MBIST can be designed at RTL level. I am not sure if that's an efficient way, because most of the proven MBIST algorithms are supported by the Industry standard tools and also some companies might have their own tools to implement MBIST at a later stage of the ASIC design. And also some memory vendors can integrate MBIST controller in their memory hard macro itself! This again is inefficient as MBIST controllers can be shared among different memories, hence these are mostly implemented at the post synthesis.
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