[DFT] IDDQ Testing Fault Coverage

[maulin sheth]

Hello all,

Why the fault coverage is high for the IDDQ Testing with less no of patterns?

Thanks & Regards,
Maulin Sheth

 

[rameshsuthapalli]

The IDDQ target is to cover maximum no of states for each logic gate in given design. we no need to observe any fault outside.
Hence is just a toggle profile. due to these reasons the IDDQ coverage is high with lesser patterns.

 

[maulin sheth]

The IDDQ target is to cover maximum no of states for each logic gate in given design. we no need to observe any fault outside.
Hence is just a toggle profile. due to these reasons the IDDQ coverage is high with lesser patterns.

Thanks for Reply.
But I am thinking that We have only 1 observe point. and that is ground or may be Power Supply current.
So is it true that we have only 1 current measure point i.e. Ground/VDD?
Pl correct me if anything wrong.
If only 1 current measuring pont thn we can detect only single fault with the single pattern.
Is it also true or not?