[DFT] IDDQ Testing Doubt

[maulin sheth]

Hello All,

During IDDQ testing,What is the observation point for the Current?
Can anyone provide good material for the IDDQ Testing?

Thanks & Regards,
Maulin Sheth

 

[rca]

During the iddq, the test is to measure the current on the digital supply. The scan chain are used to shift in a certain state to stimulate the leakage measurement.

 

[maulin sheth]

During the iddq, the test is to measure the current on the digital supply. The scan chain are used to shift in a certain state to stimulate the leakage measurement.

Thanks For Reply.
Yea That I know,I know that we measure the IDDQ current at Ground pin of top level..Pl correct me if I am wrong.
But I want to know that we have a common ground pin og chip.Means at SoC top level, we have only single Ground pin.So through single ground pin we measure the current?
Pl correct me...Because I am so much confused for the IDDQ Testing Basics.

 

[rca]

you also measure the current going through the power supply dedicated to digital instead common ground, no? By this way aou are sure to not include pad leakge for example or analog...

 

[maulin sheth]

What is the significance to measure the Power supply current?
Is the power supply current is taking as reference?
if not, thn wht is the reference point for the IDDQ current testing to compare.
ANd another thing is that,During IDDQ Testing, if we measure the current at top level Ground pin, thn the pattern size should be increased. But experiment says it is decreased with increasing the fault coverage. So, I can't understand that if we have only 1 measure/observe point for whole circuit,thn how can we meet the good fault coverage with less no of patterns.
Pl correct me if any misunderstanding happens by me.

 

[rca]

The IDDQ test is to measure the leakage of the chip at each stop point inside the patterns.
Usually up to 30-40 test points are needed for a 80% toggle iddq coverage.
This test is long, because some stabilisation time is required to measure the leakage with the same repatibility.

 

[maulin sheth]

Thanks for Reply.
30-40 test points, but I have a doubt that all are observed at the TOP level ground pin?
If yes thn,each pattern can detect only single fault...because we have only 1 observe point.
So if we have 1 observe point,how can we detect multiple faults in single pattern.
As in normal scan we are doing scan out procedure,so we can measure the faulty output at particular top level different different pins. But in IDDQ, we have only 1 observe point.