DFT compiler question

[william_qiu]

dft io pad

When I use DFT compiler to insert_scan i find if i insert_scan at chip level, I have to write a "gate level" pad model. For DFT compiler can't deal with pad correctly. The pad model i wrote contains only some AND BUF gates. But i found still sometimes DFT compiler can't understand it correctly.
Does someone know how to do DFT at chip level? Or we have to do it at core level and then hookup pads?
ThankS

 

[bendrift]

dft io site:www.edaboard.com

When I use DFT compiler to insert_scan i find if i insert_scan at chip level, I have to write a "gate level" pad model. For DFT compiler can't deal with pad correctly. The pad model i wrote contains only some AND BUF gates. But i found still sometimes DFT compiler can't understand it correctly.
Does someone know how to do DFT at chip level? Or we have to do it at core level and then hookup pads?
ThankS

--i didn't meet that it should have a pad model before insert dft! u can insert dft first and then insert io pad.

 

[william_qiu]

dft pad

When I use DFT compiler to insert_scan i find if i insert_scan at chip level, I have to write a "gate level" pad model. For DFT compiler can't deal with pad correctly. The pad model i wrote contains only some AND BUF gates. But i found still sometimes DFT compiler can't understand it correctly.
Does someone know how to do DFT at chip level? Or we have to do it at core level and then hookup pads?
ThankS

--i didn't meet that it should have a pad model before insert dft! u can insert dft first and then insert io pad.

hi bendrift
Could you give a detail description of flow?
Or could you post your script?
Thank a lot!