How do people estimate the effect of sampling switches noise on a cirсuit level? I was doing long transient simulations, than FFT and finally got PSD from which I could get the SNR and estimate SFDR.
However it seems that transistor noise source are not included in transient analyses and Matlab behavioral simulations show that the thermal noise of the switches (and thus the size of the sampling caps) is important for the performance.
Can anyone suggest a solution how to include the device noise in the final PSD of a sigma-delta modulator?
I would be most happy if you could reference me to a book which explains my question!
I thought I stated it pretty clear: how to include the effect of the sampling switches thermal noise (and OTA thermal noise) in the circuit simulation with Cadence?
The Model with support thermal Noise and Flick noise , You can check your model , AF is thermal Noise parameter , and Kf is flick noise parameter ,
In the RF model , the Model always have the two paramter , But other is zero , It don't consider these
I use hspice only, I know in hspice you can not add device noise in transient analysis. The parameter AF and KF is just for ac analysis.
I think the noise is to estimate, not to simulatie. You can reference to razavi's book for noise calculation.
You cannot add switch on resistance to
the transient simulation, the SNR that you
extract from the simulation result is related
to quantization noise and not any other noise sources
(such as shot, thermal, flicker)
In matlab your simulation result by adding
gaussian random signal to the system
can be somewhat correct, but you cannot do the same thing in hspice or cadence, because transient
time step is not constant as oppose to simulink
simulation (that introduce over or under estimation
of the added noise whit respect to the sampling instant that you choose for fft).
Only thing you can do, is the general noise analysis
of an SC integrator (dont forget to multiply the analysis result by 2 because there is a systematic error of 6dB)