Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Development & Design Eng. position available in M'sia

Status
Not open for further replies.

kcutnnuy

Newbie level 1
Joined
Aug 24, 2007
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Shah Alam
Activity points
1,454
baseline wander echo

Dear All,

Our cleint, Key ASIC is a leading fabless IC design company that designs and manufactures IC for electronics or system companies based in US, California. The company's primary technology offering is the KeySoC(TM) Platform for ASIC/SoC design-to-manufacture, targeted at reducing customer design time and enabling first time silicon success. The platform provides a high-performance ARM-based CPU platform with an extraordinary performance CPU core and memory blocks for integration of domain specific IP blocks to design ASICs or SoCs quickly. Key ASIC provides a variety of mixed-signal blocks, including video front ends for HDTV applications, high-end A/D and D/A solutions for wireless and wired communications, high-quality audio and voice codecs and peripheral interfaces for quick integration. Key ASIC ASIC service is recently nominated as EDN hot 100 products in year 2006.

They are expanding their CPU, SoCs IC Design and operations Centre in PJ, Malaysia and they are looking for talented and self-motivated individuals to expand the engineering operations.


If you are interested to apply for this position please send your CV to qflexent@gmail.com

PRODUCT/MFG DEPARTMENT


1. PRODUCT ENGINEERING MANAGER

Job Description:

The successful candidate shall be responsible for:

• Defining DFM/DFT requirement, and manufacturing flow;
• Defining test plan;
• Selecting cost effective assembly package and tester;
• Sign off of Assembly build sheet, bill of material and manufacturing route;
• Managing all prototype build, package, product and test system qualification;
• Completing product characterization before production release;
• Driving Product yield (wafer fab, wafer probe and assembly/test), manufacturing cost and quality improvement;
• Maintaining Product Definition System, Build sheet, bill of material, manufacturing route, plan yield and planning cycle time.
• Managing the resources to accomplish the above function
• Defining and executing future cost reduction / yield improvement plan.

Skills & Qualification:

Bachelor of Engineering (Electrical or electronics), B Sc in electrical engineering, electronic engineering, semiconductor device Physics, microelectronics or any related qualification with at least 5 years working experience in Mixed signal and SoC test, product, or yield engineering. Immense knowledge in product low yield investigation and problem resolution is a pre-requisite.

The position is to work independently as well as closely with engineering, sales and product marketing teams for end product development and delivery. Knowledge in wafer Fabrication and packaging assembly process will be an added advantage.


2. SENIOR PACKAGING ENGINEER

Job Description

This position will interfaces with Design Engineer, Product Engineer, Sales and Marketing engineer and manufacturing sites. The main responsibility includes but not limited to the following:

1. To define packaging design rule to accomplish manufacturing competitiveness.
2. To drive package selection, design, qualification until production release exceeding project schedule, quality and cost goal.
3. To define package specification, marking specification, packing specification.
4. To drive packaging yield, quality and cost improvement and dispose suspected material on hold in manufacturing site.

Skills & Qualification:
Bachelor of Engineering (Electrical, electronics, Mechanical, chemical), B Sc in electrical engineering, electronic engineering, semiconductor device Physics, microelectronics or any related qualification.

At least 2 years working experience in semiconductor assembly process or package development engineering and possesses excellent interpersonal skill. Candidate with Fabless semiconductor working experience will have advantages.


3. SENIOR TEST ENGINEER

As a Senior Test Engineer, you shall be required to interface with Design Engineer, Product Engineer, application engineer, third party test development and manufacturing sites. Your main job responsibility includes but is not limited to the following:

• To define test specification and manage Test development project exceeding the project schedule, quality and cost goal.
• To manage Test system transfer to manufacturing Test Site exceeding project schedule, quality and cost goal.
• To manage product quality assurance and long term assurance program for Key Asic’s product.
• To provide support to manufacturing site on suspected material disposition, Test Yield improvement and Test cost improvement Project.
• To support customer complaint.

Skills & Qualification:

Bachelor of Engineering (Electrical or electronics), B Sc in electrical engineering, electronic engineering, semiconductor device Physics, microelectronics or any related qualification.

At least 2 years working experience in semiconductor test engineering or test development, preferably in Mixed Signal or SoC products testing and possesses excellent interpersonal skill. Candidate with Fabless semiconductor working experience will have advantages.


DESIGN DEPARTMENT


1. SENIOR P&R DESIGN ENGINEERS

Job Description

In this position, you will be responsible for physical design implementation. Your scope of work includes but not limited to
• Create optimum floor plan that able to meet design specs with smaller die size.
• Power planning and IR drop analysis
• Collateral preparation for P&R
• LVS/DRC verification and fixes
• Chip integration and P&R
• ECO routing and physical optimization
• Develop P&R methodology to improve design efficiency and productivity.
• RC extraction
• CTS and timing optimization
• Custom layout editing

In this highly challenging design role, the P&R lead designer is to work with a team for the development of CPU and SoC design in 0.18 um, 0.13 um, 90nm and below technologies. Driven by high performance and low power design requirements, you need to work closely with other engineering teams and product marketing teams for end product development. Understanding of the application of the ARM cores in various domains is a plus, system SOC integration and interface needs to be continuously strengthened.

Qualifications

The ideal candidate should be knowledgeable in physical design with hands-on experience in the Block Placement and Route, Floor Planning, Chip Integration and Place & Route, Engineering Change Order (ECO), Timing Closure, Power and Clock Optimization, and Physical Verification. The candidate needs to be able to work on the entire gamut of the P&R independently. In addition to that one needs to participate in all aspects of the design flow. Hands-on experience in advanced chip design with deep sub-micron technology is a must. Power planning and optimization is critical for consumer and communication IC chips. Problem solving capability in low power design, signal integrity and cross coupling is required. The ability to work with and develop relationships with multiple function groups and execute in a fast paced environment is essential.

Required Education:

Previous experience in P&R design is required. Advanced degree in an engineering discipline is preferred.


2. CUSTOM LAYOUT DESIGN ENGINEERS

Job Description

In this position, you will be responsible for physical design implementation. Your scope of work includes but not limited to
• VLSI component layout and translation of schematics into layout geometry
• Participate in module/chip floor planning
• Physical verification includes layout extraction, LVS/DRC verification, signal integrity checks and design for manufacturing checks
• Involve in PDK development and qualification such as physical verification rules (LVS, DRC, OPC, dummification) development and qualification.
• Supports process migration across different foundries.
• Supports tapeout process and silicon debug efforts.

You will work closely with other engineering teams and product marketing teams for end product development. Understanding of library development and characterization is essential, experience in deep sub-micron layout design, integration and interface needs to be continuously strengthened.

Qualifications

The ideal candidate should be knowledgeable in custom layout design with hands-on experience in the design and development of deep sub-micron layout design and integration. He/She must be very familiar and knowledgeable with various custom layout requirements to solve the issues of fringing effect of leakage, noise, and power consumption. Exceptional knowledge from full custom layout development, characterization and timing model generation is required. Working experience in development of domain-specific application chip is a plus. The ability to work with and develop relationships with multiple function groups and execute in a fast paced environment is essential.

Required Education:

Previous experience in full custom layout development is required. Advanced degree in an engineering discipline is preferred.


3. SENIOR CUSTOM CIRCUITS ENGINEERS

Job Description

In this position, you will be responsible for physical design implementation. Your scope of work includes but not limited to
• Design in both full custom and cell-based design
• Develop high speed datapath components circuits such as adders, multipliers, shifters, etc
• Develop general purpose programmable I/Os
• Design small signal array memory and register files
• Design high speed and low power circuits
• Oversee the entire design gamut that covers RTL coding to post-layout simulation
• Participate in macro cell integration, layout design review, cell characterization, design verification, and silicon testing.
• Perform analog IPs design verification and qualification

You need to go over the entire design implementation that covers design specification to final post-layout simulation and silicon characterization. The position is to work closely with other engineering and product marketing teams for end product development. Deep understanding of the application of CPU in various domains is essential, system SOC integration and interface needs to be continuously strengthened.

Qualifications

The ideal candidate must have good knowledge in circuit and logic design with hands-on experience in the design and development of advanced CPU. Exceptional knowledge from CPU specification, design development, testing, SoC interface and integration is required. He/She must be very familiar and knowledgeable with CPU architecture, high performance and low power design. Working experience in EDA tools such as Synopsys Design Compiler, Physical Compiler, PrimeTime, etc is a plus. The ability to work with and develop relationships with multiple function groups and execute in a fast paced environment is essential.

Required Education:

BS/MS in Electrical Engineering or Computer Engineering required. Advanced degree in an engineering discipline is preferred.


4. SENIOR DESIGN FOR TEST ENGINEERS

Job Description

In this position, you will be responsible for physical design implementation. Your scope of work includes but not limited to
• Define test specification and develop test plan for SoC and CPU products.
• Develop DFT methodology for every projects
• RAM Bist development
• ATPG development
• Boundary Scan development
• Being the linkage between design team and test engineers
• Generate test patterns and bring it up with simulation and with tester
• Develop engineering test bench
• Improve design fault, test and code coverage

You need to go over the entire design implementation that covers design specification to final post-layout simulation and silicon characterization. The position is to work closely with other engineering and product marketing teams for end product development. Deep understanding of the application of CPU in various domains is essential, system SOC integration and interface needs to be continuously strengthened.

Qualifications

The ideal candidate must have good knowledge in design testing and failure analysis with hands-on experience in the design. Exceptional knowledge from product specification, design development, testing, SoC interface and integration is required. He/She must be very familiar and knowledgeable with Tetramax and VCS. The ability to work with and develop relationships with multiple function groups and execute in a fast paced environment is essential.

Required Education:

BS/MS in Electrical Engineering or Computer Engineering required. Advanced degree in an engineering discipline is preferred.


5. VoIP DESIGN MANAGER

Job Description

In this position, you will be responsible for physical design implementation. Your scope of work includes but not limited to
• Define product specification
• Product prototyping
• VoIP design creation, characterization, integration, and optimization
• VoIP system level testing and debug
• Firmware and application development
• Build up the VoIP development team

You need to go over the entire design implementation that covers the design specification to final post-layout simulation and silicon characterization. The position is to work closely with other engineering and product marketing teams for end product development. Deep understanding of the VoIP domains and system SoC integration and interface is essential.

Qualifications
The ideal candidate will have a minimum of 10 years of IC design background with 5+ years of hands-on chip design experience in VoIP. Must have direct chip design experience in the areas of Ethernet and Audio Codec. Exceptional knowledge of the QoS, Base Line Wander and Echo Cancellation is a plus. Exceptional knowledge of the VoIP system and deep understanding of this industry is required. He/She must be very familiar and knowledgeable with system architecture of CPU/DSP. High performance and low power design experience is required. Working experience in development of domain-specific application is a plus. The ability to work with and develop relationships with multiple function groups and execute in a fast paced environment is essential.
Required Education:
BS/MS in Electrical Engineering or Computer Engineering required. Advanced degree in an engineering discipline is preferred.


6. SENIOR ANALOG DESIGN ENGINEERS

Job Description

In this position, you will be responsible for physical design implementation. Your scope of work includes but not limited to
• Work with a team for the development of analog IP family that includes ADC, DAC, Audio Codec and Ethernet PHY for 130 nm, 90 nm and below technologies.
• Design creation, characterization, integration and optimization, and for system test and debug with the MII.
• Develop special analog and logic circuitry for the analog IP families.

You will go over the entire design implementation that covers design specification to final post-layout simulation, silicon characterization and test. The position is to work closely with other engineering and product marketing teams for end product development. Deep understanding of the audio and Ethernet domains is essential, system integration and interface needs to be continuously strengthened.

Qualifications

The ideal candidate will have good analog design background with 5+ years of hands-on analog design experience in the areas of ADC, DAC, Audio and Ethernet. Chip design experience in one of the areas of Audio or Ethernet PHY is a must. Exceptional knowledge of the QoS, Base Line Wander Compensation, Echo Cancellation and Adaptive Equalization is essential. Exceptional knowledge of the Audio or Ethernet system and deep understanding of this industry is required. High performance and low power design experience is required. The ability to work with and develop relationships with multiple function groups and execute in a fast paced environment is essential.

Required Education:

BS/MS in Electrical Engineering or Computer Engineering required. Advanced degree in an engineering discipline is preferred.

SENIOR RF DESIGN ENGINEERS
You will go over the entire design implementation that covers design specification to
final post-layout simulation, silicon characterization and test. The position is to work
closely with other engineering and product marketing teams for end product
development. Deep understanding of domain specific RF design in wireless application is
essential.
Responsibilities
In this position, you will be responsible for physical design implementation. Your scope
of work includes but not limited to
• Work on the design of high performance, Low Power RF circuits for IC products
that include LNAs, Mixers, Synthesizers and VCOs etc.
• RF circuit designs integration and optimization for SOC.
• RF designs silicon testing, debug and characterization.
• Develop special RF circuits for the RF IP families.
Qualifications
The ideal candidate should have the qualifications as mentioned below
• +5 years experience in RF design with good track record in high performance and
low power RF circuits such as LNA, Mixers, Synthesizer, VCO etc.
• Good knowledge of CMOS semiconductor technology processes.
• Good command of Cadence EDA tools (Virtuoso, SpectreRF, Assura etc) and
Agilent ADS etc.
• Good understanding and familiarity with RF and Mixed signal Layout techniques.
• Experience in RF designs silicon testing, debug and characterization.
• Good technical understanding of several relevant wireless standards such as IEEE
802.11 standard.
• The ability to work with and develop relationships with multiple function groups
and execute in a fast paced environment
Required Education:
BS/MS in Electrical Engineering or Computer Engineering required. Advanced degree in
an engineering discipline is preferred.


7.SYSTEM ARCHITECT

You need to go over the entire design implementation that covers the design specification
to final post-layout simulation and silicon characterization. The position is to work
closely with other engineering and product marketing teams for end product
development. Deep understanding of the system SoC integration and interface is
essential.
Responsibilities
In this position, you will be responsible for system architecture implementation. Your
scope of work includes but not limited to
• “Hands on” ownership of a significant portion of the architecture and design of a
high performance, high bandwidth, ARM processor SoC system.
• Design and develop the overall system hardware architecture
• Primary architectural focus includes microprocessor and microcontroller base
system, and industrial standard bus (PCI-E, USB2.0, SATA).
• Taking a design all the way from concept/requirements to architecture/microarchitecture
to logic design/physical implementation to bring-up/productization
• This is a very senior technical leadership position. Evangelize architecture
through the company and to customers. Help guide future technical direction and
vision.
• Invent patent key differentiated technology
• Inspire, mentor, and encourage others
Qualifications
The ideal candidate should have the qualifications as mentioned below
• 10+ years experience
• Experience in processor design and SoC design, from concept through design and
bring-up and productization
• Strong background in PCIe, USB2.0, Ethernet I/O standards and AMBA/AXI bus
architecture.
• Strong “hands on” architectural & performance modeling expertise, including
strong programming and scripting skills.
• Familiarity of system memory organizations and standards.
• Good understanding of the complete chip & system architecture & design flow
• Ideally “hands on” not only in architecture and modeling, but also RTL logic
design skills.
Required Education:
BS/MS in Electrical Engineering or Computer Engineering required. Advanced degree in
an engineering discipline is preferred.[/b]

Added after 1 hours 43 minutes:

Dear All,

Any recommendation would be appreciated!

Thanks!
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top