likewise
Newbie level 5
In Quartus, how can I determine the timing of the critical path of combinational logic, when I am still in the module design phase?
I get no Fmax report, I think because in this particular module I have no feedback from state registers to the combinational logic.
inputs=>combinational logic=>output registers=>
I get no Fmax report, I think because in this particular module I have no feedback from state registers to the combinational logic.
inputs=>combinational logic=>output registers=>