salma shabayek
Junior Member level 1
Dear all,
I am having problems solving that question:
An FPGA has an array of 128 X 128 logic elements (LEs) like the one shown below,
each with five inputs and one output. There are 129 vertical and 129 horizontal
routing channels with four segmented wires (single length) and two long wires per
channel. Each wire in the routing channel can be connected to every input of the LE
on its right and the output of the LE on its left. When two routing channels intersect,
all possible connections between the intersecting wires can be made. How many
configuration bits are required for this FPGA?
Does any one knw how to solve this?
I am having problems solving that question:
An FPGA has an array of 128 X 128 logic elements (LEs) like the one shown below,
each with five inputs and one output. There are 129 vertical and 129 horizontal
routing channels with four segmented wires (single length) and two long wires per
channel. Each wire in the routing channel can be connected to every input of the LE
on its right and the output of the LE on its left. When two routing channels intersect,
all possible connections between the intersecting wires can be made. How many
configuration bits are required for this FPGA?
Does any one knw how to solve this?
