Determine the size of the frontend sampling capacitor in ADC

[Analogworld]

Hi all,

I am wondering for a 12-bit resolution ADC, how big of a sampling capacitor at the front end should be in order to surpress the kT/C noise and opamp thermal noise from the later stages?

Peoples used 6pf before, I think it is way too big. Any ideas?

 

[yaxazaa]

Re: Determine the size of the frontend sampling capacitor in

If you are using sc sample and hold, noise may be the second issue. the first thing you need to consider is the cap mismatching. 12-bit cap mismatching may be a issue, need at least 0.001% matching requirement

 

[Analogworld]

Re: Determine the size of the frontend sampling capacitor in

Thanks for the note, are you talking about the cap matching for the MDAC in the pipelinen architecture? I think that will casue interstage gain error, but I think that can be corrected by digital calibration.

From the overall noise calculation, the sampling capacitor at the front end needs to be at least 3pf to suppress the noise below 12-bit level. Does the size of the capacitor sound right to you? Please let me know.

 

[sunking]

compare KT/C and quantization noise