Detecting logic levels with ZERO current consumption

[shaiko]

I have an electrical wire - one end goes to a logic device (FPGA/uC).
While the other end has 2 possible electrical pathes:

a.Shorted directly to ground.
b.Connected to ground through a 100KOhm resistor.

I want the logic device to detect logic high ('1') when the wire is connected to ground through the 100KOhm resistor.
I want the logic device to detect logic low ('0') when the wire is connected directly to ground.

The challenges:
1. I need zero current flow on the wire in both cases (a and b).
2. The logic levels must be stable and relatively immune to noise.

PLEASE HELP

 

[FvM]

The question title is wrong. You are not asking for detecting logic levels. The problem is about resistance measurement/detection. It's possible however to represent a logic state by a resistance value.

By nature of electric circuits, resistance can't be probed without a certain current flow. The current can DC, AC or pulsed current and must be sourced from the logic device.

An almost theoretical option is to measure the resistance by it's thermal noise. This involves microvolt voltage levels, high gain amplifiers and complex detection circuits. So it's most likely beyond the scope of your question.

 

[rahdirs]

I have an electrical wire - one end goes to a logic device (FPGA/uC).
While the other end has 2 possible electrical pathes:
View attachment 91726
a.Shorted directly to ground.
b.Connected to ground through a 100KOhm resistor.

I want the logic device to detect logic high ('1') when the wire is connected to ground through the 100KOhm resistor.
I want the logic device to detect logic low ('0') when the wire is connected directly to ground.

The challenges:
1. I need zero current flow on the wire in both cases (a and b).
2. The logic levels must be stable and relatively immune to noise.

PLEASE HELP

U could use an amplifier similar to the sense amplifier that are used in computer memory but one with an even higher gain that detects the thermal noise voltages,and use o/p of amp to make fpga generate logic level,but zero current !!!!
E[Vdet^2] = 4kTR(Δf) .

 

[shaiko]

Well...
I can allow current flaw - but not in steady state...maybe a stable voltage can be achieved with the use of capacitors ?

 

[FvM]

Dynamic meaurement is possible of course, I already presumed it by referring to AC and pulsed current. If the "logic device" is an IC, a short current pulse from a transistor would be more practical than AC coupling, I think. In any cases, there will be a clock generator, sequencer respectively state machine, drive and sense transistors.

Scan speed must be defined as a first step.

 

[shaiko]

That's exactly how I implemeted the current solution...but I was looking for something less complex

 

[chuckey]

I think that you have to define "zero current", as already mentioned, there will be thermal currents, earth loop currents and induced currents. How are you going to stop these?
Frank

 

[shaiko]

"zero current" - anything in the range of ~1nA or lower (in the steady state)

 

[pplus]

It is not clear at all. I'm trying to guess - this is some of the biological, medical, chemical probe? DUT has only two states? How much time to change the state? This is only one of the characteristics of the test device, its resistance. Resistance to assume the flow of current.
See this thread.
Nano-amp amplifier - 1nA to 1V

 

[shaiko]

No, it's not a probe.
It's an electronic circuit that's responsible of detecting the state of its inputs and respond accordingly. The device is operated from a small battery, so it needs to consume as little power possible.

 

[FvM]

It's an electronic circuit that's responsible of detecting the state of its inputs and respond accordingly. The device is operated from a small battery, so it needs to consume as little power possible.

I thought this has been obvious from the previous specification.

As a side remark, from the detection circuit's viewpoint, 100k won't be distinguished from open circuit. I guess the 100k number is more a suggestion of expected sense currents (e.g. 10 µA range). This refers to 1:10000 scan duty cycle for 1 nA input leakage (not considering internal circuit current consumption) and sounds feasible all-in-all, but doesn't permit high scan rates.