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Detect number of bit change in one clock cycle

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mpatel

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How can I write a VHDL code to detect the number of bit change..

For example I have 4 bit register A. The value of is A = 1100. Now it is changed to A=1010. So how can I detect how many bits are changed?

Is there a solution to detect in single clock pulse?

Thanks
 

kanagavel_docs

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Hi,

Please find the simple flow with verilog code

assign no_of_change = data_dly ^ data_in;

always @(posedge clk)
data_dly <= data_in;

for (i = 0; i=3; i = i+1) //it will implement the combinational logic
count = count + data_in;

this count will give you the number of changes.


Regards,
Kanags
 

srinivas_kamana

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Let Q(3 downto 0) be the output of shift register.

process(clk)
if (clk = '1' and clk'event)
if(A(3) = Q(3))
count <= count+1;
end if;
if(A(2) = Q(2))
count <= count+1;
end if;
if(A(1) = Q(1))
count <= count+1;
end if;
if(A(0) = Q(0))
count <= count+1;
end if;
end if;
end process;

So, finally this COUNT gives the no. of bit changes
 

vahidkh6222

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you can simply XOR every delayed version of a bit with it's present value, so with every change in every bit you'll suddenly detect the change(instantaneously with just a very very tiny few delay).
now you can add the resulting bits together in one clock cycle and get the number of them.

a : signal std_logic_vector(3 downto 0)
dlyd_a : signal std_logic_vector(3 downto 0)
c : signal std_logic_vector(3 downto 0)
res: signal std_logic_vector(3 downto 0)


c<= a xor dlyd_a;

process
begin
if rising_edge(clk) then
dlyd_a <= a;
res <= c(0)+c(1)+c(2)+c(3);
end if;
end process



I'm not sure about the syntax error's but you can easily modify it yourself...
 

    mpatel

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