Detect long string signal

Hi everyone,
I have three types signal: Long string signal (several us), Low Frequency Periodic Signal (30MHz) and Supper Speed signal ( 10Gps). The maximum clock I can use is 30MHz. How can I detect the long string signal with minimum delay? This image show detail the signal.

Thanks,

Low pass filter?

Or a monostable, set to time just over one cycle at 30MHz so anything slower lets it time out.

Brian.

Is your intention create an Analog design to tap off a differential signal to detect switching between 0 bps or 30 Mbps then the previous suggestions might work for you, but I suspect this is for the same 65nm CMOS ASIC in your other thread.

I think you are confused about your specifications. If your differential signal is going into an ASIC the I/O cell will most likely convert the differential signal into a single-ended logic signal, which is what you will be detecting for activity.

Most of these types of designs are for serial buses that can change their data rates. If that is the case then most of these types of protocols are designed to a) recover the clock, b) are heavily oversampled on the receive side. Given that you are switching between 30Mbps to 10Gbps lends me to believe this protocol is going to use clock recovery. This means the data will be encoded in some form on the differential line.

If the above statement is correct then you've posted this thread in the wrong section and it should be posted in the ASIC section and not in the Analog Design section.