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the function of wire load model is to estimate the interconnect delay
A wire load model describes wire load value according to the fan-out number of a net and the physical size of the block encloses the net
A wire load model consists of a set of wire load tables. Each table contains wire load data such as capacitance, resistance, and the average wire length for a series number of fan-out
normally, if you change WLM for a synthesis, the gate level netlist would be changed too, of the timing calculation will different too, as the process scalling, the interconnect delay is more and more important, so the effect maybe great.
as for VDSM process, WLM is not suitable now, so lots of other methods are provided