Details about JTAG interface

[pisoiu]

Hi,
Can anyone explain to me some details of jtag interface? I know that ieee standard have guidelines regarding signals and commands for jtag interface, but I am more interested in debugging with jtag. Each manufacturer of jtag compliant devices have some sort of simulation software for their devices, ot there are general tools, for all jtag capable devices, good for debugging with jtag interface. For example I have an fpga and a dsp in the same system, both jtag capable. Cas I use the same tools (software/cable) with both devices, or do I need specialised tool for each? thanks

 

[Big Boy]

jtag details

Well, JTAG interface basic protocol stay the same for each devices. Basically, it's a serial interface that can be chained across the different devices of a PCB.

You have 5 basic signals line:

- TMS (which is mode select)
- TCK (clock)
- TDI (Data input, input to the chip)
- TDO (Data output, data comming out of the chip)
- /TRST (Reset, this is optional. Pulling this line low reset the JTAG interface, note that it is not the same as the device reset line, and does not reset the entire device).

If you have multiple JTAG-enabled devices on a board, you can chain them, by sending each data outputs (TDO) to the next device data input (TDI). All other signals are common to all devices, i.e. tied togetter.

JTAG basic idea is that you have different JTAG 'states'. The selected state determine if you are sending/getting data from, for example, the instruction register, the data register, if you are 'capturing' data, 'updating' data, ... There are 16 states, and you switch among them depending on the TMS line when you give TCK a rising edge.

I won't explain all the details as this would get pretty long. The details may seem confusing at the begining, but it's straightforward. There are many doccuments about that that you can find on the net. One of the state, for example, is reset state. There is no JTAG functions that tell you in which state you currently are in, but whatever the state you are in, if you hold TMS high, and give 5 clock pulse (on TCK), you end-up in reset state (see here, 'startup' state). This is why /TRST is optional, as it does the same function. Once you know in which state you are, you can get to any other state, as the states machine is standard (the same across all JTAG devices). So, you start by going to reset state, and you move along from there.

In all cases, you send an instruction to the TAP (test access port, that is how that call the test-unit part of the chip), to the instruction register. Then, you read or write data to the data register.

IEEE define some commands that are mendatory for all JTAG-compliant devices, they are about 4. For a start, you can start with the IDCODE instruction (that return the device ID, that can be used to identify the device model). The exact instruction number and ID value are detailed in the device datasheet.

Be aware though that many devices implements more than just the basic mendatory instructions. Those are usually different for each devices and manufacturers often keep the information proprietary. Usually, they don't want you to know the 'debug' instructions, or else, they wouldn't make much money out of their debugging tools. This also often include boundary-scan implementations. But if you are lucky, and get access to this info (ar at least, enough info to get going), then you can do nice stuff. Sometime, some of the information leak out of the company. For example, the STi55xx chips from ST. There are some programs out there that show how to talk to part of the debug section of the chip (like reading/changing memory value). Even if this is not your intended device, you can still learn by looking at the c-files to see how to program JTAG in general (take a look at 'jtag_p' for example).

One last thing, be aware, if you implement the interface yourself, to keep TDO line away from TCK line (for example, don't run them on two consecutive wires, even if it's just a 3-inch flat cable). Put another signal in between, like TMS, TDI or even better, GND. This is a 'friendly' advice that will keep you away from trouble. I won't explain the details, but you can find a good article about the 'why' on that page: https://www.ricreations.com/AppNote003.html

Big Boy

 

[delay]

jtag chain actel

Although the interface is standardized but Xilinx JTAG won't work on Actel FPGA using Xilinx software tool set and Actel Libero software won't detect the Xilinx chips because the software driver is specific for the silicon manufacturer. I don't know if there are general software available that will detect and debug any device on JTAG.

 

[cages]

actel jtag interface

I think it is possible to test chips on A pcb that have the JTAG interface.
I have been looking into it but Have not acctualy tried using it.
There are two IEE standards one for programing chips the other for testing.(cant remeber the numbers).
look at http://www.ricreations.com/JTAG-Software-Downloads.htm and **broken link removed** both have jtag testing software.

 

[delay]

basic jtag

If your software tool for device detection allows loading the device using a BSDL file supplied by the device manufacturer, you can cenrtainly try that.