Detailed (digital) dynamic power calculation

[smarconi]

Hello,

I would like to know which tools are nowadays available for dynamic power consumption calculation. I have access to cadence tools (not all of them, for example not Palladium).
Some "requirements", hoping that somebody has experience on the field:

- it is important to simulate under realistic conditions (e.g. I know that I can import vcd in RTL compiler, at least I managed at RTL level, while it crashed after sythesis to mapped.)
- It would be ideal to get the most detailed information on power possible: I would like to understand if in digital gate level simulation (with Incisive) I can back annotate parasitics to improve power calculation including info on wire capacitance, etc... (or is it just possible to annotate timing?)

What about Voltus tool for such goals?

Many thanks,
Sara

 

[Dar89]

I don't know those tools, but, if you have the gds2 i think that you could import it in Virtuoso and making an RC extraction. In this way you obtain a spice-like netlist, which contains all the parasitic extracted and that you can simulate.

But, have you placed and routed the circuit, yet? Otherwise you could annotate switching activities on the synthesized circuits with a gate-level simulation and make a report power, after reading the vcd or tcf (is this too inaccurate for you?).

 

[smarconi]

Thank you very much for your reply. I am answering to the specific questions.

I don't know those tools, but, if you have the gds2 i think that you could import it in Virtuoso and making an RC extraction. In this way you obtain a spice-like netlist, which contains all the parasitic extracted and that you can simulate.

Moving to the analog domain is not an option, above all it should be scaled to much bigger design size. I would really prefer to avoid it.

But, have you placed and routed the circuit, yet? Otherwise you could annotate switching activities on the synthesized circuits with a gate-level simulation and make a report power, after reading the vcd or tcf (is this too inaccurate for you?).

As a "trial" I have done it for a submatrix of the whole design (which is modular). This is the initial solution I have though about (even if I still have problems at getting the gate level simulation running correctly in order to generate the vcd). Moreover, it would be ideal to annotate it with parasitics info --> I am trying it reading the spef file from encounter in RTL compiler, but did not succeed yet.

 

[rca]

voltus (ETS) is here for that, you could estimate dynamic power consumption, see on your floorplan where and what consume the power...

 

[smarconi]

voltus (ETS) is here for that, you could estimate dynamic power consumption, see on your floorplan where and what consume the power...

Thank you for your answer and for mentioning Voltus. I have not used it yet extensively (just for looking at static power and how it is distributed over the chip), and I am actually wondering how far one can go with it. I had the feeling it would have been difficult via Voltus to look at how power evolves over TIME during simulation (to find possible peaks during some simulation conditions... and so on). Could you please comment on that?

Many thanks!