DesignWare library simulation

[njr@1]

Dear all,
For the design-ware library examples to simulate and generate vcd files we would need a test-bench right !
Please also guide.

Thank you

 

[dpaul]

Ask this to yourself...
If you write the code of a 2:1 MUX, when can you say it is working properly?
Of course not b4 you have tested it, and you need a tb to test it.

The same is the case of a dw lib. For standalone fn verification you have to write a test-bench for it. Generally these dw IPs are used as part of a bigger design and they are always 'assumed' to be delivering the required functionality.

 

[njr@1]

Thank you for your kind reply.
Actually i have not written any test bench before. Where do I start from.

Please guide me.
Thank you

 

[sharath666]

A testbench is nothing but a piece of code which provides the clocks,reset and stimulus to the DUT. It also samples the output from the DUT and checks whether they are right. If they are right, it reports a success else a failure. This is what a basic testbench does.