designing PLL with integrated loop filter

[gggould]

ezpll software

Hi all,

I am going to design a 64MHz PLL with Fref=32KHz. The requirement is 1mA current budget, and everything onchip. I just run a quick matlab transfer function sim and find that with ~3kHz loop bandwidth, the conventional 3rd order rc loop filter will be too big to be integrated. I am thinking about using ring osc. and sample-hold loop filter, but not that familiar with the them. Can anyone give me some suggestions or reference papers?

Thanks a lot,

gggould
MODERATOR ACTION: Topics merged. Warning for posting same query in two forums

 

[biff44]

pll with integrated loop filter

Try some sort of capacitance multiplier, like the attached, in place of the capacitor in your RC. You should be able to get an effective capacitance of β * C. You probably need a bias resistor from collector to base (not shown).

Let me know how it simulates.

 

[eng_Semi]

integrated loop filter

3KHz is a very small BW, which will need bulky resistors and capacitors.

Try to read National Application Note AN1001, then write ur MATLAB code. From this code u will have the elements values which u will begin design, then try to dec the cap and watch the PM and the phase noise, till u reach the best solution. If the cap is still big, try to use gate capacitance (in order to get use of its large density)

What is the calculated value of the cap, and will u use a 2nd or 3rd order filter ??

 

[greenfrog]

Re: designing 60MHz PLL with integrated loop filter??

Hi all,

I am going to design a 64MHz PLL with Fref=32KHz. The requirement is 1mA current budget, and everything onchip. I just run a quick matlab transfer function sim and find that with ~3kHz loop bandwidth, the conventional 3rd order rc loop filter will be too big to be integrated. I am thinking about using ring osc. and sample-hold loop filter, but not that familiar with the them. Can anyone give me some suggestions or reference papers?

Thanks a lot,

gggould

i am same curious on the value of your computeed caps and ressitors, could you post them for sharing? and what is the area you estimate to use for cap and resistor? thanks

 

[gggould]

Re: designing 60MHz PLL with integrated loop filter??

3KHz is a very small BW, which will need bulky resistors and capacitors.

Try to read National Application Note AN1001, then write ur MATLAB code. From this code u will have the elements values which u will begin design, then try to dec the cap and watch the PM and the phase noise, till u reach the best solution. If the cap is still big, try to use gate capacitance (in order to get use of its large density)

What is the calculated value of the cap, and will u use a 2nd or 3rd order filter ??

Thank for your feedback, I really appreciate.

The reason I choose 3khz BW is because the Fref is only 32KHz. The BW can only be less than 32K/10.
I have ever use a nice software called EZPLL provided by National to estimate the loop filter size. With reasonable PM, the C1 is about 700pF and barely changes when I change the filter order, which is way to large to be integrated.
As for using big MOS cap, my concern is about the gate leakage current.

I am considering other loop filter topology, such as sample-hold. But don't have any experience on that...

 

[gggould]

Re: designing PLL with integrated loop filter??

Try some sort of capacitance multiplier, like the attached, in place of the capacitor in your RC. You should be able to get an effective capacitance of β * C. You probably need a bias resistor from collector to base (not shown).

Let me know how it simulates.

Thanks for you feedback. But the BJT is not available in my CMOS process.

I have find one paper talking about the capacitance multiplier. But my concern is will those active mosfets generate lots of noise on the vtune line...

A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier
Keliu Shu; Sanchez-Sinencio, E.; Silva-Martinez, J.; Embabi, S.H.K.;
Solid-State Circuits, IEEE Journal of
Volume 38, Issue 6, June 2003 Page(s):866 - 874

Btw, do you have any experience about using sample-hold loop filter?

 

[biff44]

Re: designing PLL with integrated loop filter??

Never used a sample and hold loop filter. Not sure what they are. But I do know that if you sample too slowly, or add too much time lag with a digital process, in linear terms it is like adding control loop phase shift--and your control loop loses phase margin stability.

Mosfets can be noisy, but they are the most noisy when then are operated in large signal (nonlinear) mode. If you are using them as a linear voltage follower amplifier as a C multiplier, the noise MIGHT be manageable. Depends on what ultimate synthesizer phase noise you are looking for.

 

[eng_Semi]

Re: designing 60MHz PLL with integrated loop filter??

The reason I choose 3khz BW is because the Fref is only 32KHz. The BW can only be less than 32K/10.

I know that this is suitable value for the loop BW as long as the ref. frequency is equal to 32KHz.

I have ever use a nice software called EZPLL provided by National to estimate the loop filter size. With reasonable PM, the C1 is about 700pF and barely changes when I change the filter order, which is way to large to be integrated.
As for using big MOS cap, my concern is about the gate leakage current.

700pF !!!!! :!: it is a very large value :|

U may have two solutions, which are:
1. To use a capacitor multiplier circuit.
2. U can switch to a fractional-N PLL, so u can increase the BW, but it will not heavily increase, it will increase to the order of 10 Kohms