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designing of ultralow power 16 bit sigma delta ADC

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naomi

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hi

I am designing a 16 bit sigma delta ADC in cadence. I am not able to design a decimation filter in CMOS... can any one suggest me any circuit
 

willyboy19

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You can find how to build the decimation filter in many DSP books. Typical implementation involves ROM/RAM based controller plus a MAC unit. The filter coefficients can be easily found in MATLAB filter design tools.
 

nickooeda

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you first learn "signal and system", then "using Matlab",then "Verilog",then .....
 

tucura

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A decimation filter uses a Cascaded-Integrator-Comb section
followed by a FIR section. The CIC section decimates down to 4
times the output sampling frequency and has a response of the
form (sin x over x)^n, n being higher than the order of the analog
section. The FIR can be any linear phase design, and is used for
antialias pourposes. If the clock frequency is less than, say 10 MHz,
power is very low (uW).
 

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