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Designing of Photodiode Layout in 0.18u CMOS process

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ammadupm

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Hi,
I would like to draw the layout of photo-diode in Hynix 0.18u CMOS process.
Plz help.....
 

erikl

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Use a p+ in N-well structure: photodiode_cross_section.png Also check this thread!
 

dick_freebird

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Behind the basics there are some nuances that relate to
things like suppressing / minimizing RTS (RTN) noise, field
control and so on. Applications which need very low dark
current and cryo operation care a lot about this; a receiver
for short haul fiber optics, less so.

Give some thought to your application care-abouts, and
the literature may help you with the finer points of device
construction.
 

ammadupm

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PD sch.pngPD layout.png

Can you check this Schismatic and layout of the Photo-diode.............Is this correct?
 

erikl

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You just need one photodiode in layout: the other one (in schematic) is a parasitic diode between n-well and substrate. See this image:
The area of the parasitic diode (the n-well area) is bigger than the pd (the p+) area.

The quadratic structure outside around the p+ diffusion area is the border between two recognition areas, s. this post.
 

ammadupm

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Plz check this now..........
I draw the layout as explained by erikl, but may be few errors are still in LVS check.......
PD.png
 

erikl

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Seems ok. If (and which) recognition layers are necessary for the LVS check to match, depends on your PDK's extract rules.

You wouldn't need the extra n-well contact, the n+ guard ring contacts are enough. So you could save some area: the n-well diffusion area can be with min. spacing outside the n+ guard ring, and the p+ substrate guard ring may have min. spacing to the n-well.
 
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