Designing Flyback Converter

[7f6grenade]

So, I have been trying to simulate a flyback converter to understand its working in depth so I can move to QR Flyback converters later. There are a few issues I am facing with modelling which I am really struggling to solve after trying a lot of values and placements.

1. I am not able to get Vplateau match with my theoretical value of Vin + nVout as the simulation shows Vplateau to be much greater than what I calculated but additionally Vplateau keeps increasing with each cycle for some reason and stabilizes at some ~600V value which is much greater than my calculated 270V.
2. I am facing some problems with my snubber circuit, I calculated the values using the Design Guidelines for RCD Snubber of Flyback Converters by FairChild but those values dont really give promising results in terms of damping the leakage ringing.
3. At one point, I was getting the plateau before high frequency ringing followed by resonance ringing which just confused as to how the order can be changed in comparison to the expected Vds waveform I should have got.

Would appreciate if I can know what are my pitfalls and oversights which I can improve on and learn from, thanks!

 

[24vtingle]

Your secondary inductance is too low, giving you too high peak sec current, and also, it means there is too much voltage getting referred from sec to pri.
Also, you use the MBRS140 40V Schottky twice, and in both cases, it is getting overvoltaged.
Also you use only 30V fet, and it has a few hundred volts on it.

To do leakage properly, you really need to have it in pri and sec. Suppose you measure 1uH of leakage in pri.....then you should make the "leakage inductor" 500nH in pri in sim...and L(leakage) for sec is then 500nH x (NS/NP)^2

 

[BradtheRad]

problems with my snubber circuit,

DCR snubber is frequently used. It's like attaching a buck-boost converter to the primary winding. It must use up energy coming from the primary's high voltage spike at the moment of switch shut-off.

Too low RΩ permits current flowing too long after switch is shut off (wastes Watts).

Too high RΩ puts excessive burden on C.

Too low C uF causes charge V to rise alarmingly. It's reasonable to keep it no greater than supply V.

Easy guideline for RC combination: choose values so the RC time constant fits within switch-Off time.

 

[24vtingle]

Yes and also as attached is some more about it

 

[7f6grenade]

Thank you so much, I have made the Ls about 7u now for a turn ratio of 6.
Can you please suggest what diode and fet should I be using in place of these ? Does anything with Vds > 500 for FET and I am not sure about what replacement I can use for the diode

Your secondary inductance is too low, giving you too high peak sec current, and also, it means there is too much voltage getting referred from sec to pri.
Also, you use the MBRS140 40V Schottky twice, and in both cases, it is getting overvoltaged.
Also you use only 30V fet, and it has a few hundred volts on it.

To do leakage properly, you really need to have it in pri and sec. Suppose you measure 1uH of leakage in pri.....then you should make the "leakage inductor" 500nH in pri in sim...and L(leakage) for sec is then 500nH x (NS/NP)^2

 

[24vtingle]

Best to use an ultra fast diode, and for the FET, just something where the rds(on) will be ok.

 

[7f6grenade]

Best to use an ultra fast diode, and for the FET, just something where the rds(on) will be ok.

I am able to get better output now, thank you so much for the help. I just was facing some problems with Rsnub and Csnub, so by calculating using the resources given above in the thread, I get R about 56Ohms and C about 2.2uF but this time constant is too large in comparison to my Toff of 20us, so I generally used a 1KOhm resistor and 10nF capacitor which seems to work but I still cannot show this theoretically. Is there anything wrong am I doing in my calculations?

 

[24vtingle]

..well some of the energy from the leakage goes into the cap across the fet...and that then gets dissipated in the fet when the fet switches on.
Also some of the power dissipated in the R of the RCD clamp is just from the reflected voltage thrown onto it from the secondary side,
Many people put a TVS in the RCD clamp so that at start up or transients, the RCD clamp voltage does not go too high.

I even saw one 150W non PFC'd offline flyback and they didnt even bother with a rcd clamp!.....the 650V FET was getting 820V pk on it when on full load!

It survived because those systems usually spend all their life in standby, and the 820vpk then does not occur....i ran it in the lab with 820Vpk on the 650V fet for three hours....and it did not blow up.....the FET must have been dealing with it by avalanching but its not recomended.
I was forced to put this into production with no changes...ie just stay with the 820vpk, ....for their sake, not mine. i refused to do this...and my contract was terminated.

 

[7f6grenade]

So, my converter seems to be working on the surface with generally waveforms matching expected behavior. I need to find power loss due to different components in the converter now, for which I am currently trying to find the damping caused by the internal resistance of leakage inductor in the high frequency ringing that happens just after switch is off. The issue is that:
a. When trying to find how much power the leakage inductor is dissipating, LTSpice gives me a negative value due to the sinusoidal shape that the power waveform follows.
I need to show that the internal resistance of the leakage inductor dissipates some energy before it is transferred to parasitic capacitor and then compare that when I use a snubber circuit, how much energy is dissipated by the Rsnubber and Rseries of the leakage inductor damping the oscillations of the high freq ringing faster.
So, the approach I was taking was to calculate using LTSpice Alt+Left-Click tool and then finding the integral of that power waveform across the time period when the high frequency ringing happens to get energy in microjoules. The issue is that these energies are not adding up, i.e the energy dissipated by the Rsnub and the Cparasitic and the internal resistance of the leakage inductor should add upto the energy dissipated by the leakage inductor as a whole, but since that value is in negative, I am a bit lost how to model this out and show the effect of my snubber circuit on power loss.

 

[FvM]

Dissipated power should never show negative, you obviously did something wrong, e.g. probing the wrong voltages and current.
Ltspice has a nice efficiency calculation feature that lists loss contribution of individual components. It depends on detecting circuit periodic steady state, the detector is built-in to several LT switcher controllers but can be also generally used, check respective articles on the net.

Regarding snubber dimensioning, you first need to identify the resonant circuit you want to dampen, e.g. Cds,off and transformer Ls. Determine resonance frequency and characteristic impedance. For maximal effect, Rsnub should be in the range of characteristic impedance. C as small as possible, e.g. in the range of Cds.

 

[24vtingle]

Sorry to be negative, but strays are a significant part of snubber loss calcs....so whatever you calc, you will need to verify in the hardware anyway. So people usually just throw in a space for a 3W power resistor, then just use say a 1W resistor if the dissipation was not actually so high.
If you interleave wind a flyback, then the snubber loss is usually lower than any shortform calcualtion gives it.

High power flybacks (300W+) can use a small flyback in the RCD snubber itself to regenerate the energy from the leakage L back to the primary side capacitor.

Remember your S->P referred voltage can give a big part of the loss in the RCD clamp resistor ("RCD clamp" AKA "primary snubber" AKA "primary clamp")

 

[FvM]

RCD snubber has the primary purpose to absorb stored Ls energy and reduce overshoot that might exceed transistor voltage rating. If your circuit shows distinct oscillations, they can be better dampened by a RC snubber. Calculation of both snubber types is quite different, I was referring to RC snubber only because it seems appropriate for your circuit conditions at first sight. Looking at your Ltspice simulation circuit, I'm not sure if the parameters are realistic, also some components are unsuitable, e.g. low voltage Schottky for primary RCD.

 

[7f6grenade]

I have tried to implement a lot of feedback given in the thread. The major thing I am struggling with now is understanding why the high frequency ringing caused by L_leak and C_para die out in my simulation so fast? What other things am I missing which contribute in this daming beside R_leak which I have modelled

Additionally, when I join the snubber circuit, it seems to dissipate such large energy amounts which are larger than what the inductor and capacitor even stored initially, so what energy is it even dissipating?

And for snubber dimensions, when I use the theoretical formulas to get Zchar which should be root of (Lleak/Cpara) and use that value, the Vds waveform just kills any ringing at all which means I also do not get valleys which are important for switching in the converter.

Would appreciate if I can get help in these modelling parameters for my flyback! (Have attached the updated model)

 

[Easy peasy]

why the high frequency ringing caused by L_leak and C_para die out in my simulation so fast?

what are the R parameters for the cap and the winding ? Is there a snubber on the diode on the sec side ? this will add damping.

--- Updated Jun 9, 2025 ---

Do you have some clear PDF's of the schematics ? with detail

 

[7f6grenade]

what are the R parameters for the cap and the winding ? Is there a snubber on the diode on the sec side ? this will add damping.

--- Updated Jun 9, 2025 ---

Do you have some clear PDF's of the schematics ? with detail

I had explicitly made the ESR of all capacitances 0 and series resistance of all inductors 0 too because I was under the impression that leakage resistance of the leakage inductor which I have modelled outside it might be the most important contributor in damping the oscillations which doesnt seem to be the case.

Additionally, for the snubber at the output, I am not sure but I added it because in absence of that resistor, Vds peak seems to keep increasing with time which would just make my FET explode, with that resistor Vds peak seemed to be constant after each switching and also the high frequency ringing time period further reduces without the resistor at the output. It was about 7us before and then drops down to 4us if removed. which might suggest that damping has increased without the resistor which shouldnt be the case as this ringing happens when the FET is off and the diode in secondary side is FB meaning the Rout should also add into damping as it dissipates energy too.

 

[24vtingle]

With a simulation , say LTspice, the device capacitances with voltage are not properly modelled...also the skin effect characteristic of all conductors isnt modelled, also, the losses due to core losses of all that HF ringing are not modelled. As such, it wont be possible to get much great accuracy off the sim.

.......i have just opened your schem of post #13 and you have used gen purpose silicon diodes instead of ultra fast ones. As such, you will see all manner of problems

You used the "RFN5TF8S" for the sec diode , unless of course my LTspice has subbed it in without telling me.....that does sometimes happen.

OK, that diode is is fact coming up as a ultra fast diode in its datasheet, but LTspice depicts it as an "Si " diode...which would mean a slow diode....so it needs the model for it to be looked at....best to use a diode that LTspice calls a "fast diode".

RFN5TF8S

https://fscdn.rohm.com/en/products/databook/datasheet/discrete/diode/fast_recovery/rfn5tf8s.pdf

Having said that, there is a special technique involving use of a slow Si diode for the RCD clamp, but that requires specialist attention.

 

[7f6grenade]

That makes sense. So, to just to clear out, the high frequency ringing caused by L-Leak and C-parasitic dies out because of the combination of a lot of small resistances and capacitances which are not modelled in LTSpice and hence it would be very difficult for me to accurately tell what is causing the damping.
This means I can just generally infer that the damping happens faster with a snubber meaning my snubber is working atleast but the efficiency of the snubber would be difficult to calculate accurately?

With a simulation , say LTspice, the device capacitances with voltage are not properly modelled...also the skin effect characteristic of all conductors isnt modelled, also, the losses due to core losses of all that HF ringing are not modelled. As such, it wont be possible to get much great accuracy off the sim.

.......i have just opened your schem of post #13 and you have used gen purpose silicon diodes instead of ultra fast ones. As such, you will see all manner of problems

You used the "RFN5TF8S" for the sec diode , unless of course my LTspice has subbed it in without telling me.....that does sometimes happen.

OK, that diode is is fact coming up as a ultra fast diode in its datasheet, but LTspice depicts it as an "Si " diode...which would mean a slow diode....so it needs the model for it to be looked at....best to use a diode that LTspice calls a "fast diode".

RFN5TF8S

https://fscdn.rohm.com/en/products/databook/datasheet/discrete/diode/fast_recovery/rfn5tf8s.pdf

Having said that, there is a special technique involving use of a slow Si diode for the RCD clamp, but that requires specialist attention.

 

[24vtingle]

Here is your ~100W flyback edited to bring the pk sec current down , and the primary clamp dissip down....and a few other alterations
I kept your vout virtually the same as what you had it (~23v)

 

[7f6grenade]

Here is your ~100W flyback edited to bring the pk sec current down , and the primary clamp dissip down....and a few other alterations
I kept your vout virtually the same as what you had it (~23v)

Thank you so much, will try to do simulations on this and let you know.

Edit: Just wanted to clarify, I cannot see any resonance valleys being created by Lprimary and Cparasitic that would be required for me to model this into a QR Flyback. Is there anything I can do about it?

 

[Easy peasy]

often you have to add a small cap across the Tx, or across the mosfet to get full QR operation - in the real world a high capacitance style wdg of the Tx pri will give you sufficient capacitance - remember the sec side snubber will damp any ring - so make this as light as possible - i.e. low leakage Tx and fast diode.