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Designing CMOS Logic Circuits from Boolean Functions

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purifier

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I've been thinking a lot on this. My lecturer explained the CMOS implementation of NAND and NOR and NOT but that was only using the switch model. But i was wondering how to design the circuit if it is a bigger function say AB'+A'B or something like that. I need a logical process through which i can design a CMOS circuit given a boolean function. Can someone help me? Please help...
 

Hi

Look for cgen.
It is one answer to your question.
If you failed to obtain the code. I have it in my archive and I will upload it upon request.


CGEN: A symbolic layout generator for static CMOS circuits.


tnx
 

Thank you for the reply.. but i don't have any idea about that CGEN... COuld you help me out please?
 

First get the function into SOP or some standarat for .Then using NAND NOT NOr .for the circuit as these r universal functions.
 

You would have to design PUN (Pull Up Network) and PDN (Pull Down Network) expressions from the logic function. Remember thatn PDN and PUN are the duals of each other e.g.
Dual of AB'+A'B is
(A'+B).(A+B')

where the former one will form PDN while the later one PUN.
 

purifier said:
Thank you for the reply.. but i don't have any idea about that CGEN... COuld you help me out please?


Hi
here it is
CGEN source code +paper

BTW: Here is the old yet online direct link for download:

1. h**p://www.cs.utah.edu/~mbinu/coursework/ee6740/

* -> t

tnx
 

Sorry .. but does this program works only on the sun machines ?? i.e. isnt it also available for windows environment ?

I hope i can find one for windows ...

thanks
 

You would have to design PUN (Pull Up Network) and PDN (Pull Down Network) expressions from the logic function. Remember thatn PDN and PUN are the duals of each other e.g.
Dual of AB'+A'B is
(A'+B).(A+B')

where the former one will form PDN while the later one PUN.

I guess this would be helpful to me... Can you elaborate it please...
 

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