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designing a Voltage clamp with GCNMOS

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sharas

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gcnmos

Hi,

I have to design a voltage clamp using a gate-coupled NMOS and a resistor between the gate to the ground. I need to be able to hold the gate voltage on more than 1.6V for 20n sec. Can anybody advise me how to choose the right RC, and after that: how to choose the value of R&C. What should be my design methodology?

Thanks in advance,

Sharas
 

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