A ) In normal syn FIFO design, the data out is not registered.
assign data_out = MEM[RD_PTR];
B) If we would like to register the data_out as
always @(posedge clk)
data_out <= MEM[RD_PTR];
Compared the method, the B (registered data_out) will read out the data_out 1 clk cycle slower than method A.
In my design I have to design the FIFO with the registered data_out but without the 1clk cycle delay as shown at Method B.
I heard there's some design technics called pre-pop, anyone has any idea of this ? Please advice!
I am no expert but this is my idea. Pros please feel free to correct me.
In your code. The READ_PTR in Ex.A is most probably being incremented synchronously with the clock and !wr/rd signals. So there is still 1 clk cycle delay in the entire read process.
now consider this for Ex.B
Code:
always @(posedge clk)
if (!wr)
begin
data_out <= MEM[READ_PTR];
READ_PTR <= READ_PTR + 1;
end
so the read pointer is updated in this clock cycle and all set up for the next read which is when rd/!wr is asserted.
U just need a pre-read logic, and Register to hold the data u read last time
pre-read logic: when rd is assert, raddr = nxt_rtpr// read the next data
there is problem , that is when FIFO is empty, and wr happen, so the FIFO depth=1
but there is no read happen, so u need to read the first data out into REG that u can use the value in REG when read happen. After that, every read operation read the next data in FIFO and store it in REG