fysloc
Newbie level 1
I have an issue with trying to figure out how to implement a simple switch (as in OPEN or CLOSE circuit) in verilog.
Some background: I have a device that takes user button presses (mostly a capacitive switch) and I have a design that will automatically "press buttons" given certain conditions. The plan I have is to make a small module that can be copied for as many buttons there are.
Heres how my current design works for a single module:
Given the positive end of the switch and ground, wires are soldered onto these end and fed through the FPGA, in which I wrote a simple switch module that takes the positive end as the input, another signal to trigger the switch as input, and the ground as output. Then, my conditional statement is a very simple if statement:
always @ (*)
begin: BUTN_OUT
if (butn_trigger == 1)
ground = pos_input;
else
ground = 0;
end
For a single implementation, this works (afterall, its just acting as a wire between the pos_input and ground), but the moment I try to add this to a top level with more than 1 button, I run into the signal driven by multiple drivers error, mostly due to me driving ground to 0 in my original module.
I know that ground shouldnt be driven in my module, but I can't really think of another way of doing this given my limited knowledge of Verilog. Any help would be appreciated.
PS. The ground is different from the FPGA supply and ground, if that makes a difference.
Some background: I have a device that takes user button presses (mostly a capacitive switch) and I have a design that will automatically "press buttons" given certain conditions. The plan I have is to make a small module that can be copied for as many buttons there are.
Heres how my current design works for a single module:
Given the positive end of the switch and ground, wires are soldered onto these end and fed through the FPGA, in which I wrote a simple switch module that takes the positive end as the input, another signal to trigger the switch as input, and the ground as output. Then, my conditional statement is a very simple if statement:
always @ (*)
begin: BUTN_OUT
if (butn_trigger == 1)
ground = pos_input;
else
ground = 0;
end
For a single implementation, this works (afterall, its just acting as a wire between the pos_input and ground), but the moment I try to add this to a top level with more than 1 button, I run into the signal driven by multiple drivers error, mostly due to me driving ground to 0 in my original module.
I know that ground shouldnt be driven in my module, but I can't really think of another way of doing this given my limited knowledge of Verilog. Any help would be appreciated.
PS. The ground is different from the FPGA supply and ground, if that makes a difference.