Designing a high voltage bandgap

[tyanata]

Can any one give me an advice or paper for designing high voltage bandgap reference. The technology is 0.35lv. The bandgap voltage has to be at 4.6 volts VDD=5V.

I tried circutit shown in file bandgap, but bandgap voltage is lower from the desired level-VBG=4V.

Another approach, is to use the circuit in file bandgap_2 where R1 is the same type resistor as the resistor in bias cicuit, and R2 is different type resistor with different TC1. In this way it is possible to obtain bandgap volktage at the desired level, but the dependence from process variatons is very large.

 

[Fom]

Re: High voltage bandgap

Why do you call this bandgap?
To get advice you should give whole schematic. Because the output voltage level and it's temperature coefficient will depend on bias circuit also.

To get 4.6V from 5V use a combination of standard bangap and OP amp, like in LDO design.

 

[tyanata]

Bias

That is bias circuit. M1 and M2 are in saturation, M3 and M4 are in weak inversion to obtain temperature dependent current.

You are right that it is mistake to call the circuit bandgap, it it is voltage reference.

We don't want to use Op Amp after ordinary bandgap, to avoid amplification of offsets caused process variations or missmatches or whatever.

 

[tsanlee]

High voltage bandgap

The TC of MOS Vt is not the same as VBE.
The PTAT Current can not cancel the VBE (NTAT)
The design can not get the good TC spec.

You can add 1:4 or 1:8 BJT under M3 and R1,this circuit can produce a PTAT current form delta VBE
.

 

[andy2000a]

High voltage bandgap

what i your means Hi Volt bandgap ??
if you need power_ok or UVLO(under Low volt lock )
at 4.6v , I suggest use bandgap = 1.25v

and use compartaor + resistor volt divider , but should be note , power_ok maybe start_up fail
when Vcc < 3v , becuase Vcc < 3v Bandgap circuit is fail but COMP work , and create "Fake" UVLO signal

 

[tyanata]

Re: High voltage bandgap

Tsanlee wrote:

The TC of MOS Vt is not the same as VBE.
The PTAT Current can not cancel the VBE (NTAT)
The design can not get the good TC spec.

You can add 1:4 or 1:8 BJT under M3 and R1,this circuit can produce a PTAT current form delta VBE

Yes, you are rigth that, it is better to use Iptat bias instead of bias stage with NMOS in weak inversion. But the bias current is not problem, the real problem is refference voltage level Vref≈3*Vbe+3*0.6 ≈4V, but I need 4.6V.

 

[leonken]

Re: High voltage bandgap

the temp. coefficient value of Vgs are always same when Vgs works in weak inversion. saturation region or moderate region?

 

[tyanata]

Re: High voltage bandgap

Yes, but the tempreture dependence of the current is different for tranzistors in saturation and weak inversion.

 

[kwkam]

High voltage bandgap

Usually, bandgap or voltage reference is not strong enough to drive any circuits input. Therefore, a voltage buffer is required. And typical offset voltage of a good design buffer is under 5mV. If you can't live at this offset voltage. You better think about the overall design is reasonable or not.