Design without verification

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i saw ppl design without modelSim in FPGA design. it's possible but need to have a lot experience
 
ur design should meet ur requirement. during synthesis u can find wether u meet the timing requirements or not. but u cant check ur expected out without functional verification. coz everyone is not perfect. hence it always preferbale to do coding first in modelsim and later synthesize ur design

thanks and regards
deepak
 

It is possible for small design which are designed for combo logic.
But not possible for big designs having multiple logic in the design which have to follow timing/place constraints.
 

ya, but use quartus II
 

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