Design Verification question

[gold_kiss]

Hi,
What do we mean by self checking testbench. Can any one help me in understanding as to how I can built such a testbench say for a small digital design.

Thanks in advance,
Gold_kiss

 

[radix]

A self checking testbench is one that compares the designs behavior during simulation with some expected behavior.

One way to generate a self-checking test bench is to have a file with the expected output for a given input vector file. The testbench would read both files, apply the vectors from the input file and then compare the generated outputs with the expected data from the output file.

A lot of places actually do the checking after a simulation run. The simulation will generate an output file which some post-processor (like a perl script) will compare against the expected output file.

 

[qjlsy]

except for result checking, bus monitor should also be included in self-checking scope.

 

[zhangpengyu]

Hi
It's include some concepts:generation, constrain,check,coverage.You could see the book
<writing testbenches>
zhpy

 

[kermit]

where can i find the version 2 <how to write testbech>?

 

[spauls]

Self checking testbench compares the behavior during execution with similar expected behavior.

U can have input vector in the form of C or text file and collect output vectors in different file and compare.
Perl is best, u can use TCL/TK to make ur verification plan GUI based.

 

[rol73]

I'm adding a little note:

You can generate the expected outputs vector from a high abstraction level behavioral model of your chip; using a functional coverage tool, you can create an outputs vector which ensures totally the chip logic correct work...

 

[qjlsy]

just comparing the seqence and data of 2 verctors is not enough!!!

 

[rol73]

I'm talking of functional correctness: in this field, the matter is the vectors choice... a functional coverage tool can help you to choose input patterns that involve virtually all expected outputs from your block...

 

[AlexWan]

If you want to build a automatic test enviornment, you can use the display error in your test cases and assertion in your RTL design.

Pls refer h**p://www.verificationlib.org

or following PDF

 

[ram]

The self checking test bench takes the input data ...applies the DUT alogoritm on it or may use proven IP..takes output form DUT compares this DUT output with the calculted output from input. The comman term used is scoreboarding