Jul 9, 2008 #1 C chled Newbie level 1 Joined Jul 9, 2008 Messages 1 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,285 Hi, I' m getting a bit confused, in logic synthesis how do we fix the violated design rule constraint which are max capacitance, max transition and max fanout?
Hi, I' m getting a bit confused, in logic synthesis how do we fix the violated design rule constraint which are max capacitance, max transition and max fanout?