Re: Design procedure
if you're concerned about noise, you can use the rule of thumb that Vn^2 = 4kT*Cc, where Cc is the compensation capacitor - for either Miller or Ahuja (indirect) compensation, and size the capacitor.
Also knowing the value of Cc and having a transient or a unity gain bandwidth specification you can get the value of the gm of the diff pair.
You can size the output stage for the Slew-Rate but also be carefull that it affects the location of the RHP (right half plane) zero and the non-dominant pole.
With the values of gm's you can size the current bias to supply the required current but also be aware that a large different in the currents of the first and second stage can make the first stage output node to slew, as it sees a big capacitance (Cgs of the second-stage gain transistor).
This is one way of designing two-stage opamps. Note that this is an iterative process, as everything is related, and also that if you use cascoding, the transient response is more complex
Hope this helps