Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Design procedure of opamps - need clarification

Status
Not open for further replies.

Snik

Newbie level 4
Joined
Apr 19, 2009
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,337
Design procedure

Hi dear all,
i confused with design procedure of opamps that should compensate with compensation capacitor(except load compensation such as folded cascode).
i some opamps similar to "two stage", for designing opamp we must use of some requierments and then start to sizing transistors. but for slew rate that is so important for opamps, we must at first now the value of compensation capacitor(it means that before starting the design and before finding output frequency charactristic, we supposed to knew value of compensation capacitor). i really mixed up about it. please clarify me and help me for understandig this issue.

Thx in advance
 

culho

Newbie level 6
Joined
May 13, 2008
Messages
14
Helped
2
Reputation
4
Reaction score
1
Trophy points
1,283
Activity points
1,362
Re: Design procedure

if you're concerned about noise, you can use the rule of thumb that Vn^2 = 4kT*Cc, where Cc is the compensation capacitor - for either Miller or Ahuja (indirect) compensation, and size the capacitor.
Also knowing the value of Cc and having a transient or a unity gain bandwidth specification you can get the value of the gm of the diff pair.
You can size the output stage for the Slew-Rate but also be carefull that it affects the location of the RHP (right half plane) zero and the non-dominant pole.
With the values of gm's you can size the current bias to supply the required current but also be aware that a large different in the currents of the first and second stage can make the first stage output node to slew, as it sees a big capacitance (Cgs of the second-stage gain transistor).
This is one way of designing two-stage opamps. Note that this is an iterative process, as everything is related, and also that if you use cascoding, the transient response is more complex

Hope this helps
 

    Snik

    Points: 2
    Helpful Answer Positive Rating

shady205

Full Member level 2
Joined
Oct 1, 2006
Messages
120
Helped
3
Reputation
6
Reaction score
0
Trophy points
1,296
Location
India Bangalore
Activity points
2,058
Re: Design procedure

Please find the Detailed analysis and design of two stage Opamp in analog integrated Circuits by Laker and Sansen.
Even in Analog IC Design by Ken Martin

---

ShaDy205
 

    Snik

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top