Continue to Site

# design problem of hysteresis inverter!

Status
Not open for further replies.

#### gdhp

##### Advanced Member level 4
hi all

i am designing a hysteresis inverter. The structure is composed of three

inverter. The power is 3.3v. The up and down triger voltage are about 0.5v and

1.1v.

Can anyone give some suggestions about how to modify the triger volage?

and can some give some materestrials?

Thank you!

adjust the W/L about I2 and I4

hi sunking
can you explain it in detail? thanks!

you can simulate the schematic with dc input (in)

plot I1 input and vout.

pay attention to the transfer voltage of I3 I5 and I2 I4 is difference

### gdhp

Points: 2
first thankyou sunking

i have do the simulation.and have adjust the circuit to get the trigger voltage.

but the waveform of the output is very bad and the delay is large. so can you tell me how to minimize the delay? what control the delay time ?

have some any materials about the histeresis inverter?

hi gdhp
the switching threshold voltage of an inv is determined by the kn/kp of the nmos and pmos FET. when out is 1, I2 is off and I4 is on and parallel to I5; when out is 0, I4 is off and I2 is on and parallel to I3. Values of kn/kp in these 2 condition are different, so the trigger voltages.
refer to cmos schmitt trigger section of rabaey's 'digital integrated circuits' for detail.
to reduce the delay, make the W/L of transistors larger.

### gdhp

Points: 2
hi vale
i think the delay is not only determined by w/l. because in the histeresis inverter, there is a feedback.

any suggestion?

gdhp said:
hi vale
i think the delay is not only determined by w/l. because in the histeresis inverter, there is a feedback.

any suggestion?
that's positive feedback controling voltage switching point, not related to delay.
what are the W/L values of L2 inverter?

hi vale
the W/L is 2/0.34 adn 6/0.34 of L2 inverter.

In my circuit, the delay is about 2-4ns, it is too large to my requiment.

But if i increase the W/L, the current is also large, it is not my wish.

so i am puzzled!

Added after 22 minutes:

i think the wL of L2 is is too large!thank you vale!

try to reduce gate areas of fets in L2.
It may be a heavy cap load of the preceding inverter.
again refer to rabaey's book for optimizing cascaded inverters

gdhp said:
hi vale
the W/L is 2/0.34 adn 6/0.34 of L2 inverter.

In my circuit, the delay is about 2-4ns, it is too large to my requiment.

But if i increase the W/L, the current is also large, it is not my wish.

so i am puzzled!

Added after 22 minutes:

i think the wL of L2 is is too large!thank you vale!

How about decrease the lenth of all transistor?
Did you try it?

Status
Not open for further replies.