Design of Random Access Memories using verilog or vhdl

[MEDIPALLY NAVEEN KUMAR]

how to design random access memories using verilog or vhdl? and what is the tool we have to use for it? is it possible with model sim?

please respond to my answer as soon as possible.

thank you..

 

[jeet_asic]

You can use Questasim by Mentor Graphics. Nice tool. Probably its possible with modelsim too.