design of PMOS common source amplifier 3.3V 20dB 1-10kHz

[Ugur Yegin]

PMOS common source amp.

Hi there,

We are trying to implement a PMOS only common source amplifier (both amplifying transistor and its load must be pmos) with a 20 db amplification based on a 350nm technology (AMS 0.35um). The whole thing is planned to operate with 3.3V supply voltage and must amplify ~1-10mV signals with a frequency range of 1-10kHz fed into its input, while keeping the noise levels as low as possible. The whole circuitry is going to be part of a high-density circuitry, which means that I have to operate under space limitations. Since I'm new to analog, I would first get some expert views from you here . Anyone any suggestions regarding the design, W/L ratios, layouting, tips with the cadence simulation?

Thanks

Ugur

 

[mads]

PMOS common source amp.

start with reasonable width and length twice of Lmin. plot the vin vs vout and fix the operating point so that current, transconductance etc. are in the range. finally you can tune gain, current etc. by varying the lenght and width. Analog design environment in cadence may help you to do these.

 

[Ugur Yegin]

Is it actually possible at all to design a CS amplifier with a PMOS device as the input transistor, while still reaching similar voltage gains as with the NMOS amplifiers? All examples I have found so far use an NMOS as the input device, but we would like to try the PMOS approach due to its better noise qualities. If anyone could post a schematic or example to get me started, it would be highly appreciated.

Thanks

Ugur