Design of High Side Gate Driver IC

[nonlocality]

Hi All,

As part of my master's thesis I am designing an integrated SMPS. It will include all the gate drivers and MOSFETS on a single chip. I need to use bootstrapped gate drivers for my high side switches. Could anybody point me to any books or papers describing how these are designed? (I am not asking for an ebook/pdf, just give me the name of the paper, I can access most papers through my institution).

To be clear, I am not asking what bootstrapping is, nor how to implement it on a PCB. I am asking how the gate driver IC itself is designed.

 

[treez]

You mean like one of these chips..
https://ac-dc.power.com/products/hiper-family/hipertfs-2/

..what you are asking, the “silicon floor planning” of it, well, I always assumed that was secret info held in top security by those fab houses who know it

 

[nonlocality]

Hi There,

That is the type of IC I am talking about.

I am not asking about the floorplanning/layout specifically. What I'm more interested in is a block diagram, explaining the key components, and why they are needed, and perhaps how they are typically interested.

 

[treez]

Well the attached LTspice simualtion shows a typical current mode controller with its guts ripped out so you can probe each thing.....
Oscillator
RS Latch
Gate driver
FET
PWM comparator
Error amplifier
Voltage references
etc etc
I assume you know why all the above are included in a typical smps control chip

- - - Updated - - -

The bootstrap diode and bootstrap cap are never usually integrated onto the chip.
The signal translator is on the chip though, and this is to pass the signal from the grounded control chip's reference to the high-side...it could be like in a digital isolator, or like a capacitive transfer, etc

 

[FvM]

You'll find a bootstrap driver IC functional circuit and a HV CMOS cross-section in IRF AN-978.

 

[mtwieg]

Typically the level shifting is done by converting input edges into narrow pulses which are sent over high voltage level shifters, which are then decoded with SR latches on the high voltage side.

After a quick search on IEEE, literature is somewhat sparse on the subject, but here are a couple papers that might interest you:
https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7313884
https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7056464
https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7282160